Methods and structures that include a vertical-transport field-effect transistor. A first section of a dielectric layer is deposited on a first device region of a substrate and a second section of the dielectric layer is deposited on a second device region of the substrate. A gate stack is deposited on the first device region and the second device region. The gate stack is patterned to define a first gate electrode of the vertical-transport field-effect transistor on the first section of the dielectric layer and a second gate electrode of a high-voltage field-effect transistor on the second section of the dielectric layer. The first section of the dielectric layer is a spacer layer arranged between the first gate electrode and the first device region. The second section of the dielectric layer is a portion of a gate dielectric arranged between the second gate electrode and the second device region.