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201 条记录 (耗时 0.022 秒)

    Dual metal-insulator-semiconductor contact structure and formulation method
    2.
    发明授权
    Dual metal-insulator-semiconductor contact structure and formulation method 有权

    公开(公告)号：US10535606B2

    公开(公告)日：2020-01-14

    申请号：US16040752

    申请日：2018-07-20

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

    发明人： Takashi Ando ,  Hiroaki Niimi ,  Tenko Yamashita

    IPC分类号： H01L23/528 ,  H01L23/535 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/768 ,  H01L29/51 ,  H01L29/66

    摘要： A method of making a semiconductor device includes forming a first source/drain trench and a second source/drain trench over a first and second source/drain region, respectively; forming a first silicon dioxide layer in the first source/drain trench and a second silicon dioxide layer in the second source/drain trench; forming a first source/drain contact over the first source/drain region, the first source/drain contact including a first tri-layer contact disposed between the first silicon dioxide layer and a first conductive material; and forming a second source/drain contact over the second source/drain region, the second source/drain contact including a second tri-layer contact disposed between the second silicon dioxide layer and a second conductive material; wherein the first tri-layer contact includes a first metal oxide layer in contact with the first silicon dioxide layer, and the second tri-layer contact includes a second metal oxide layer in contact with the second silicon dioxide layer.

    Test structure macro for monitoring dimensions of deep trench isolation regions and local trench isolation regions
    3.
    发明授权
    Test structure macro for monitoring dimensions of deep trench isolation regions and local trench isolation regions 有权

    公开(公告)号：US10396000B2

    公开(公告)日：2019-08-27

    申请号：US14789476

    申请日：2015-07-01

    申请人： International Business Machines Corporation ,  Globalfoundries, Inc.

    发明人： Tenko Yamashita ,  Chun-Chen Yeh ,  Hui Zang

    IPC分类号： H01L21/66 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088

    摘要： Embodiments are directed to a method Embodiments are directed to a test structure of a fin-type field effect transistor (FinFET). The test structure includes a first conducting layer electrically coupled to a dummy gate of the FinFET, and a second conducting layer electrically coupled to a substrate of the FinFET. The test structure further includes a third conducting layer electrically coupled to the dummy gate of the FinFET, and a first region of the FinFET at least partially bound by the first conducting layer and the second conducting layer. The test structure further includes a second region of the FinFET at least partially bound by the second conducting layer and the third conducting layer, wherein the first region comprises a first dielectric having a first dimension, and wherein the second region comprises a second dielectric having a second dimension greater than the first dimension.

    INTEGRATION OF VERTICAL-TRANSPORT TRANSISTORS AND PLANAR TRANSISTORS
    4.
    发明申请
    INTEGRATION OF VERTICAL-TRANSPORT TRANSISTORS AND PLANAR TRANSISTORS 审中-公开

    公开(公告)号：US20190214307A1

    公开(公告)日：2019-07-11

    申请号：US15868199

    申请日：2018-01-11

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Ruilong Xie ,  Chun-chen Yeh ,  Kangguo Cheng ,  Tenko Yamashita

    IPC分类号： H01L21/8234 ,  H01L27/088

    摘要： Structures including a vertical-transport field-effect transistor and a planar field-effect transistor, and methods of forming such structures. First and second sacrificial fins are respectively formed over first and second areas of the first device region. One or more semiconductor fins of the vertical-transport field-effect transistor are formed over the second device region. A first gate electrode of the planar field-effect transistor, which is arranged on the first device region between the first sacrificial fin and the second sacrificial fin, and a second gate electrode of the vertical-transport field-effect transistor, which is wrapped about the one or more semiconductor fins, are currently formed.

    NANOSHEET DEVICES WITH CMOS EPITAXY AND METHOD OF FORMING
    6.
    发明申请
    NANOSHEET DEVICES WITH CMOS EPITAXY AND METHOD OF FORMING 审中-公开

    公开(公告)号：US20190019733A1

    公开(公告)日：2019-01-17

    申请号：US16133850

    申请日：2018-09-18

    申请人： GLOBALFOUNDRIES INC.

    发明人： Ruilong Xie ,  Cheng Chi ,  Pietro Montanini ,  Tenko Yamashita ,  Nicolas Loubet

    IPC分类号： H01L21/8238 ,  H01L27/092

    CPC分类号： H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092

    摘要： This disclosure relates to a method of forming nanosheet devices including: forming a first and second nanosheet stack on a substrate, the first and the second nanosheet stacks including a plurality of vertically spaced nanosheets disposed on the substrate and separated by a plurality of spacing members, each of the plurality of spacing members including a sacrificial layer and a pair of inner spacers formed on lateral ends of the sacrificial layer; growing a pair of epitaxial regions adjacent to the first and second nanosheet stacks from each of the plurality of nanosheets such that each of the plurality of inner spacers is enveloped by one of the epitaxial regions; covering the first nanosheet stack with a mask; and forming a pair of p-type source/drain regions on the second nanosheet stack, each of the pair of p-type source/drain regions being adjacent to the epitaxial regions on the second nanosheet stack.

    Vertical pillar-type field effect transistor and method
    7.
    发明授权
    Vertical pillar-type field effect transistor and method 有权

    公开(公告)号：US10158021B2

    公开(公告)日：2018-12-18

    申请号：US15873935

    申请日：2018-01-18

    申请人： GLOBALFOUNDRIES INC.

    发明人： Ruilong Xie ,  Kangguo Cheng ,  Tenko Yamashita

    IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L23/535 ,  H01L21/768 ,  H01L29/417 ,  H01L21/311

    摘要： Disclosed is a method of forming a vertical pillar-type field effect transistor (FET). One or more semiconductor pillars are formed by epitaxial deposition in one or more openings, respectively, that extend through a first dielectric layer and that have high aspect ratios in two directions. The first dielectric layer is etched back and the following components are formed laterally surrounding the semiconductor pillar(s): a first source/drain region above and adjacent to the first dielectric layer, a second dielectric layer on the first source/drain region, a gate on the second dielectric layer and a gate cap on the gate. The gate cap extends over the top surface(s) of the semiconductor pillar(s). A recess is formed in the gate cap to expose at least the top surface(s) of the semiconductor pillar(s) and a second source/drain region is formed within the recess. Also disclosed is the vertical pillar-type FET structure.

    INTEGRATION OF VERTICAL-TRANSPORT TRANSISTORS AND HIGH-VOLTAGE TRANSISTORS
    9.
    发明申请
    INTEGRATION OF VERTICAL-TRANSPORT TRANSISTORS AND HIGH-VOLTAGE TRANSISTORS 审中-公开

    公开(公告)号：US20180342507A1

    公开(公告)日：2018-11-29

    申请号：US15604932

    申请日：2017-05-25

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Ruilong Xie ,  Chun-Chen Yeh ,  Kangguo Cheng ,  Tenko Yamashita

    IPC分类号： H01L27/088 ,  H01L29/66 ,  H01L29/40 ,  H01L29/417 ,  H01L29/51 ,  H01L29/78

    摘要： Methods and structures that include a vertical-transport field-effect transistor. A first section of a dielectric layer is deposited on a first device region of a substrate and a second section of the dielectric layer is deposited on a second device region of the substrate. A gate stack is deposited on the first device region and the second device region. The gate stack is patterned to define a first gate electrode of the vertical-transport field-effect transistor on the first section of the dielectric layer and a second gate electrode of a high-voltage field-effect transistor on the second section of the dielectric layer. The first section of the dielectric layer is a spacer layer arranged between the first gate electrode and the first device region. The second section of the dielectric layer is a portion of a gate dielectric arranged between the second gate electrode and the second device region.