An array board 11b includes a gate line 19, a TFT 17, a pixel electrode 18, a display pixel PX, and a second interlayer insulation film 27. The TFT 17 includes a gate electrode 17a formed from a part of the gate line 19, a channel section 17d formed from an oxide semiconductor film 24, a source section 17b connected to one end of the channel section 17d, and a drain section 17c connected to another end of the channel section 17d and formed from the oxide semiconductor film 24 having resistance lower than the channel section 17d. The pixel electrode 18 is connected to the drain section 17c. The display pixel PX includes the TFT 17 and the pixel electrode 18. The second interlayer insulation film 27 has a second hole in a position overlapping the pixel electrode and the drain section 17c and not overlapping the gate electrode 17a.