公开(公告)号：US20230335061A1

公开(公告)日：2023-10-19

申请号：US18028710

申请日：2020-10-02

Applicant: Sharp Kabushiki Kaisha

Inventor： Nobuyuki TAYA ,  Makoto YOKOYAMA ,  Naoki UEDA

IPC: G09G3/3266 ,  G11C19/28 ,  G09G3/3233

CPC classification number: G09G3/3266 ,  G09G3/3233 ,  G11C19/287 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/041 ,  G09G2320/043

Abstract: The scanning line drive circuit has a configuration in which a plurality of unit circuits are connected in multiple stages. A unit circuit includes: a first transistor having a first conductive terminal to which a first-level voltage is applied and a second conductive terminal connected to a first node; a second transistor having a second conductive terminal to which a second-level voltage is applied; a third transistor having a first conductive terminal connected to the first node and a second conductive terminal connected to a first conductive terminal of the second transistor; a fourth transistor having a first conductive terminal connected to a control terminal of the third transistor, and having a second conductive terminal and a control terminal to both of which the second-level voltage is applied; and an output transistor having a control terminal connected to the first node and a second conductive terminal connected to an output terminal.

公开(公告)号：US20190362673A1

公开(公告)日：2019-11-28

申请号：US16477555

申请日：2017-09-25

Applicant: Sharp Kabushiki Kaisha

Inventor： Naoki UEDA

IPC: G09G3/3233 ,  H01L27/32 ,  G09G3/3266 ,  G09G3/3275

Abstract: The present application discloses to provide a display device capable of displaying an image with a luminance depending on a data signal by controlling pulling of a gate voltage of a driving transistor occurring when a writing period starts and ends and a driving method of the display device.A pixel circuit including a compensation circuit compensating variation of a threshold value of a driving transistor is provided with a boost capacitor including a MOS capacitor between a node connected to a gate terminal of the driving transistor and a scanning line. A current value of a drive current is controlled by the driving transistor by using the pulling of the potential of the node being different between a case that a low level voltage is applied the scanning line connected to the boost capacitor and a case that a high level voltage is applied.

公开(公告)号：US20170235173A1

公开(公告)日：2017-08-17

申请号：US15509526

申请日：2015-08-31

Applicant: Sharp Kabushiki Kaisha

Inventor： Sumio KATOH ,  Naoki UEDA

IPC: G02F1/1368 ,  H01L29/786 ,  H01L27/12 ,  G02F1/1362 ,  G02F1/1343

CPC classification number: G02F1/1368 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/136209 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/134372 ,  G02F2001/136218 ,  G02F2201/121 ,  G02F2201/123 ,  G02F2202/02 ,  G02F2202/10 ,  H01L21/28 ,  H01L27/1225 ,  H01L27/1248 ,  H01L29/786 ,  H01L29/7869

Abstract: A semiconductor device includes: a first metal layer including a gate electrode; a first insulating layer provided on the first metal layer; an oxide semiconductor layer provided on the first insulating layer; a second insulating layer provided on the oxide semiconductor layer; a second metal layer provided on the oxide semiconductor layer and the second insulating layer, the second metal layer including a source electrode; a third insulating layer provided on the second metal layer; and a first transparent electrode layer provided on the third insulating layer. The oxide semiconductor layer includes a first portion lying above the gate electrode and a second portion extending from the first portion so as to lie across an edge of the gate electrode on the drain electrode side. The third insulating layer does not include an organic insulating layer. The second insulating layer and the third insulating layer have a first contact hole which overlaps the second portion of the oxide semiconductor layer when viewed in a normal direction of the substrate. The first transparent electrode layer includes a transparent electrically-conductive layer which is in contact with the second portion of the oxide semiconductor layer in the first contact hole.

公开(公告)号：US20180348560A1

公开(公告)日：2018-12-06

申请号：US15779103

申请日：2017-02-17

Applicant: Sharp Kabushiki Kaisha

Inventor： Seiichi UCHIDA ,  Kuniaki OKADA ,  Naoki UEDA ,  Takahiro SASAKI

IPC: G02F1/1368 ,  G02F1/1362 ,  G02F1/1335 ,  H01L23/532 ,  H01L27/12 ,  H01L29/423 ,  H01L29/08

CPC classification number: G02F1/1368 ,  G02F1/133345 ,  G02F1/133512 ,  G02F1/133514 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2201/123 ,  G02F2201/40 ,  G09F9/30 ,  H01L23/5329 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/0847 ,  H01L29/42384 ,  H01L29/78618 ,  H01L29/78633 ,  H01L29/7869

Abstract: An array board 11b includes a gate line 19, a TFT 17, a pixel electrode 18, a display pixel PX, and a second interlayer insulation film 27. The TFT 17 includes a gate electrode 17a formed from a part of the gate line 19, a channel section 17d formed from an oxide semiconductor film 24, a source section 17b connected to one end of the channel section 17d, and a drain section 17c connected to another end of the channel section 17d and formed from the oxide semiconductor film 24 having resistance lower than the channel section 17d. The pixel electrode 18 is connected to the drain section 17c. The display pixel PX includes the TFT 17 and the pixel electrode 18. The second interlayer insulation film 27 has a second hole in a position overlapping the pixel electrode and the drain section 17c and not overlapping the gate electrode 17a.

公开(公告)号：US20180341138A1

公开(公告)日：2018-11-29

申请号：US16052670

申请日：2018-08-02

Applicant: Sharp Kabushiki Kaisha

Inventor： Sumio KATOH ,  Naoki UEDA

IPC: G02F1/1368 ,  H01L29/786 ,  G02F1/1343 ,  G02F1/1362 ,  H01L21/28 ,  H01L27/12 ,  G02F1/1333

CPC classification number: G02F1/1368 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/136209 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/134372 ,  G02F2001/136218 ,  G02F2201/121 ,  G02F2201/123 ,  G02F2202/02 ,  G02F2202/10 ,  H01L21/28 ,  H01L27/1225 ,  H01L27/1248 ,  H01L29/41733 ,  H01L29/786 ,  H01L29/7869

Abstract: A semiconductor device includes: a first metal layer including a gate electrode; a first insulating layer provided on the first metal layer; an oxide semiconductor layer provided on the first insulating layer; a second insulating layer provided on the oxide semiconductor layer; a second metal layer provided on the oxide semiconductor layer and the second insulating layer, the second metal layer including a source electrode; a third insulating layer provided on the second metal layer; and a first transparent electrode layer provided on the third insulating layer. The oxide semiconductor layer includes a first portion lying above the gate electrode and a second portion extending from the first portion so as to lie across an edge of the gate electrode on the drain electrode side. The third insulating layer does not include an organic insulating layer. The second insulating layer and the third insulating layer have a first contact hole which overlaps the second portion of the oxide semiconductor layer when viewed in a normal direction of the substrate. The first transparent electrode layer includes a transparent electrically-conductive layer which is in contact with the second portion of the oxide semiconductor layer in the first contact hole.

公开(公告)号：US20160358567A1

公开(公告)日：2016-12-08

申请号：US15117507

申请日：2015-02-10

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Masahiro TOMIDA ,  Naoki UEDA

IPC: G09G3/36 ,  G02F1/1343 ,  G02F1/1368 ,  H01L29/24 ,  H01L29/786 ,  H01L29/423 ,  H01L29/417 ,  G02F1/133 ,  H01L27/12

CPC classification number: G09G3/3648 ,  G02F1/13306 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/13454 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/133302 ,  G02F2201/123 ,  G02F2202/10 ,  G09G2310/0291 ,  G09G2310/08 ,  G09G2320/0214 ,  G09G2330/021 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/3276 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/42356 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78696

Abstract: An active matrix substrate (100) includes a display region (R1) in which a plurality of pixels are provided and a frame region (R2) provided around the display region, the frame region including a plurality of peripheral circuit TFTs (5) which are constituents of a driving circuit, wherein each of the plurality of peripheral circuit TFTs includes a gate electrode (12), a source electrode (16), a drain electrode (18), and an oxide semiconductor layer (14), and in at least some of the plurality of peripheral circuit TFTs, a source connecting region (Rs) that is a connecting region between the oxide semiconductor layer and the source electrode and a drain connecting region (Rd) that is a connecting region between the oxide semiconductor layer and the drain electrode are asymmetrically provided.

Abstract translation: 有源矩阵基板（100）包括其中设置有多个像素的显示区域（R1）和围绕显示区域设置的框架区域（R2），所述框架区域包括多个外围电路TFT（5） 驱动电路的构成要素，其中，所述多个外围电路TFT中的每一个包括栅电极（12），源电极（16），漏电极（18）和氧化物半导体层（14），至少 多个外围电路TFT中的一些，作为氧化物半导体层和源电极之间的连接区域的源极连接区域（Rs）和作为氧化物半导体层和源极电极之间的连接区域的漏极连接区域（Rd） 漏电极是不对称的。

公开(公告)号：US20160293613A1

公开(公告)日：2016-10-06

申请号：US15037077

申请日：2014-08-15

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Sumio KATOH ,  Naoki UEDA

IPC: H01L27/112 ,  G02F1/1368 ,  H01L27/12 ,  G09G3/36 ,  H01L29/786 ,  H01L29/417

CPC classification number: H01L27/11206 ,  G02F1/1368 ,  G09G3/3655 ,  G09G2300/0426 ,  G09G2300/08 ,  G09G2300/0842 ,  H01L27/101 ,  H01L27/1225 ,  H01L27/1251 ,  H01L29/41733 ,  H01L29/78678 ,  H01L29/7869

Abstract: A semiconductor device includes a memory transistor (10A) which is capable of being irreversibly changed from a semiconductor state where drain current Ids depends on gate voltage Vg to a resistor state where drain current Ids does not depend on gate voltage Vg. The memory transistor (10A) includes a gate electrode (3), a metal oxide layer (7), a gate insulating film (5), and source and drain electrodes. The drain electrode (9d) has a multilayer structure which includes a first drain metal layer (9d1) and a second drain metal layer (9d2), the first drain metal layer (9d1) being made of a first metal whose melting point is not less than 1200° C., the second drain metal layer (9d2) being made of a second metal whose melting point is lower than that of the first metal. Part P of the drain electrode 9d extends over both the metal oxide layer (7) and the gate electrode (3) when viewed in a direction normal to a surface of the substrate. The part (P) of the drain electrode (9d) includes the first drain metal layer (9d1) and does not include the second drain metal layer (9d2).

Abstract translation: 半导体器件包括能够从漏极电流Ids取决于栅极电压Vg的半导体状态不可逆地改变为漏极电流Ids不依赖于栅极电压Vg的电阻状态的存储晶体管（10A）。 存储晶体管（10A）包括栅极（3），金属氧化物层（7），栅极绝缘膜（5）以及源极和漏极。 漏电极（9d）具有包括第一漏极金属层（9d1）和第二漏极金属层（9d2）的多层结构，第一漏极金属层（9d1）由熔点以下的第一金属构成 第二漏极金属层（9d2）由熔点低于第一金属的第二金属制成。 当从垂直于衬底表面的方向观察时，漏电极9d的部分P在金属氧化物层（7）和栅电极（3）上延伸。 漏电极（9d）的部分（P）包括第一漏极金属层（9d1），不包括第二漏极金属层（9d2）。

公开(公告)号：US20160247579A1

公开(公告)日：2016-08-25

申请号：US15028240

申请日：2014-09-02

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Naoki UEDA ,  Sumio KATOH

IPC: G11C17/16 ,  H01L29/10 ,  H01L27/112 ,  H01L29/786 ,  H01L29/423 ,  G11C17/18 ,  H01L29/24

CPC classification number: G11C17/16 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C17/18 ,  G11C19/184 ,  G11C19/28 ,  G11C2213/15 ,  G11C2213/53 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/11206 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/42356 ,  H01L29/7869

Abstract: A memory cell (101) includes a memory transistor (10A) having channel length L1 and channel width W1, and a plurality of select transistors (10B) each electrically being connected in series with the memory transistor and independently having channel length L2 and channel width W2, wherein each of the memory transistor and the plurality of select transistors includes an active layer (7A) formed from a common oxide semiconductor film, the memory transistor is a transistor which is capable of being irreversibly changed from a semiconductor state where drain current Ids depends on gate voltage Vg to a resistor state where drain current Ids does not depend on gate voltage Vg, and channel length L2 is greater than channel length L1.

Abstract translation: 存储单元（101）包括具有沟道长度L1和沟道宽度W1的存储晶体管（10A），以及多个选择晶体管（10B），每个选择晶体管与存储晶体管串联连接，独立地具有沟道长度L2和沟道宽度 W2，其中存储晶体管和多个选择晶体管中的每一个包括由公共氧化物半导体膜形成的有源层（7A），所述存储晶体管是能够从半导体状态不可逆地改变的晶体管，其中漏极电流Ids 取决于栅极电压Vg到漏极电流Ids不依赖于栅极电压Vg并且沟道长度L2大于沟道长度L1的电阻器状态。

公开(公告)号：US20230112313A1

公开(公告)日：2023-04-13

申请号：US17908003

申请日：2020-03-02

Applicant: Sharp Kabushiki Kaisha

Inventor： Masahiro MITANI ,  Makoto YOKOYAMA ,  Naoki UEDA

IPC: G09G3/3266 ,  G09G3/3291 ,  G09G3/325

Abstract: Provided is a scanning-line driving circuit configured with a plurality of unit circuits cascaded in stages and integrally formed with a display panel. The unit circuit includes a first transistor, a resistor, a second transistor, and an output transistor. The first transistor has a first conductive electrode supplied with a first-level voltage and a second conductive electrode connected to a first node. The resistor is connected to the first node at a first terminal. The second transistor has a first conductive electrode supplied with a second-level voltage and a second conductive electrode connected to a second terminal of the resistor. The output transistor has a control electrode connected to the first node and a first conductive electrode connected to an output terminal. The resistor is formed in a semiconductor layer. The unit circuit further includes an upper electrode formed above the resistor. This configuration allows the scanning-line driving circuit to prevent an operation failure due to a change in characteristics of the resistor in the unit circuit.

公开(公告)号：US20220392402A1

公开(公告)日：2022-12-08

申请号：US17770402

申请日：2019-10-31

Applicant: Sharp Kabushiki Kaisha

Inventor： Naoki UEDA ,  Ryohei MORITA

IPC: G09G3/325 ,  G09G3/3291

Abstract: The present application discloses a current-driven display device of an internal compensation type in which threshold compensation of a drive transistor is appropriately performed without causing a decrease in display quality or a decrease in yield during manufacturing, and display luminance is improved while a drive voltage is maintained. A pixel circuit 15 in the display device includes first and second drive transistors M1a, M1b, and the gate terminals thereof are connected to each other and connected to a holding capacitor Cs. During the data write period, a voltage of a corresponding data signal line Dj is written to the holding capacitor Cs via the first drive transistor M1a, having been set in a diode connection mode by a threshold compensation transistor M3, to perform data writing accompanied by threshold compensation. During the emission period, a current corresponding to the sum of currents I1, I2 flowing through the first and second drive transistors M1a, M1b in accordance with the holding voltage of the holding capacitor Cs is supplied to an organic EL element OL as a drive current Id.