- 专利标题: Semiconductor Epitaxy Bordering Isolation Structure
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申请号: US16043286申请日: 2018-07-24
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公开(公告)号: US20180350601A1公开(公告)日: 2018-12-06
- 发明人: Wen-Chin Chen , Cheng-Yi Wu , Yu-Hung Cheng , Ren-Hua Guo , Hsiang Liu , Chin-Szu Lee
- 申请人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 主分类号: H01L21/20
- IPC分类号: H01L21/20 ; H01L29/66 ; H01L29/04 ; H01L21/02
摘要:
A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.
公开/授权文献
- US10522353B2 Semiconductor epitaxy bordering isolation structure 公开/授权日:2019-12-31