公开(公告)号：US10957540B2

公开(公告)日：2021-03-23

申请号：US16719311

申请日：2019-12-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wen-Chin Chen ,  Cheng-Yi Wu ,  Yu-Hung Cheng ,  Ren-Hua Guo ,  Hsiang Liu ,  Chin-Szu Lee

IPC分类号： H01L31/102 ,  H01L21/00 ,  H01L21/20 ,  H01L29/66 ,  H01L29/04 ,  H01L21/02 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165 ,  H01L21/306

摘要： A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.

公开(公告)号：US09899210B2

公开(公告)日：2018-02-20

申请号：US14918009

申请日：2015-10-20

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Ren-Hua Guo ,  Ju-Ru Hsieh ,  Jen-Hao Yang

IPC分类号： H01L21/31 ,  H01L21/02 ,  C23C16/455 ,  C23C16/458 ,  C23C16/46 ,  C23C16/50 ,  C23C16/52 ,  H01L29/66 ,  C23C16/44 ,  C23C16/509 ,  H01L21/8238

CPC分类号： H01L21/02271 ,  C23C16/4401 ,  C23C16/45565 ,  C23C16/4557 ,  C23C16/458 ,  C23C16/46 ,  C23C16/50 ,  C23C16/5096 ,  C23C16/52 ,  H01L21/02315 ,  H01L21/8238 ,  H01L21/823871 ,  H01L29/165 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

摘要： A method for manufacturing a semiconductor device includes forming a transistor on a substrate. Precursor gases are provided from a showerhead of a chemical vapor deposition (CVD) apparatus to form a contact etch stop layer (CESL) to cover the transistor and the substrate. A temperature of the showerhead is controlled in a range of about 70° C. to about 100° C. to control a temperature of the precursor gases.

公开(公告)号：US11088150B2

公开(公告)日：2021-08-10

申请号：US16259824

申请日：2019-01-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yu-I Shih ,  Ren-Hua Guo

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/11 ,  H01L29/165 ,  H01L21/3065 ,  H01L29/04

摘要： A method includes forming a semiconductor fin over a substrate; forming a plurality of isolation structures adjacent to the semiconductor fin; etching the semiconductor fin to form a recess between the isolation structures; forming a first epitaxy layer in the recess; forming a second epitaxy layer over the first epitaxy layer; forming a third epitaxy layer over the second epitaxy layer, in which the first epitaxy layer has a higher germanium (Ge) concentration than the second and third epitaxy layers; etching the third epitaxy layer; and forming a dielectric layer in contact with the third epitaxy layer after etching the third epitaxy layer.

公开(公告)号：US20180350601A1

公开(公告)日：2018-12-06

申请号：US16043286

申请日：2018-07-24

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wen-Chin Chen ,  Cheng-Yi Wu ,  Yu-Hung Cheng ,  Ren-Hua Guo ,  Hsiang Liu ,  Chin-Szu Lee

IPC分类号： H01L21/20 ,  H01L29/66 ,  H01L29/04 ,  H01L21/02

摘要： A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.

公开(公告)号：US11621268B2

公开(公告)日：2023-04-04

申请号：US17394914

申请日：2021-08-05

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yu-I Shih ,  Ren-Hua Guo

IPC分类号： H01L21/02 ,  H01L27/11 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L21/3065 ,  H01L29/04

摘要： A method includes forming a first semiconductor fin over a p-well region of a substrate; forming a second semiconductor fin over an n-well region of a substrate; forming a gate structure crossing the first semiconductor fin and the second semiconductor fin; performing an implantation process to form a source/drain doped region in the first semiconductor fin; etching the second semiconductor fin to form a recess therein; performing a first epitaxy process to grow a first epitaxy layer in the recess; performing a second epitaxy process to grow a second epitaxy layer over the first epitaxy process; etching the second epitaxy layer to round a corner of the second epitaxy layer; forming an interlayer dielectric (ILD) layer covering the first semiconductor fin and the second epitaxy layer, wherein no etching is performed to the first semiconductor fin after forming the gate structure and prior to forming the ILD layer.

公开(公告)号：US20210210350A1

公开(公告)日：2021-07-08

申请号：US17205715

申请日：2021-03-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wen-Chin Chen ,  Cheng-Yi Wu ,  Yu-Hung Cheng ,  Ren-Hua Guo ,  Hsiang Liu ,  Chin-Szu Lee

IPC分类号： H01L21/20 ,  H01L29/66 ,  H01L29/04 ,  H01L21/02 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165

摘要： A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.

公开(公告)号：US10522353B2

公开(公告)日：2019-12-31

申请号：US16043286

申请日：2018-07-24

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wen-Chin Chen ,  Cheng-Yi Wu ,  Yu-Hung Cheng ,  Ren-Hua Guo ,  Hsiang Liu ,  Chin-Szu Lee

IPC分类号： H01L21/20 ,  H01L29/66 ,  H01L29/04 ,  H01L21/02 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165 ,  H01L21/306

摘要： A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.

公开(公告)号：US11930628B2

公开(公告)日：2024-03-12

申请号：US18295249

申请日：2023-04-03

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yu-I Shih ,  Ren-Hua Guo

IPC分类号： H10B10/00 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

CPC分类号： H10B10/12 ,  H01L21/02293 ,  H01L21/3065 ,  H01L21/823821 ,  H01L29/045 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7853 ,  H01L29/7854

摘要： A device includes a substrate, a pull-down transistor over the substrate, a pass-gate transistor over the substrate, and a pull-up transistor over the substrate. The pull-up transistor includes a first gate structure and first source/drain epitaxy structures on opposite sides of the first gate structure, in which each of the first source/drain epitaxy structures comprises a first epitaxy layer and a second epitaxy layer over the first epitaxy layer, wherein a germanium concentration of the first epitaxy layer is higher than a germanium concentration of the second epitaxy layer.

公开(公告)号：US11658032B2

公开(公告)日：2023-05-23

申请号：US17205715

申请日：2021-03-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wen-Chin Chen ,  Cheng-Yi Wu ,  Yu-Hung Cheng ,  Ren-Hua Guo ,  Hsiang Liu ,  Chin-Szu Lee

IPC分类号： H01L29/78 ,  H01L21/331 ,  H01L21/20 ,  H01L29/66 ,  H01L29/04 ,  H01L21/02 ,  H01L29/08 ,  H01L29/165 ,  H01L21/306

CPC分类号： H01L21/2022 ,  H01L21/02002 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/0262 ,  H01L21/02381 ,  H01L21/02502 ,  H01L21/02516 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02636 ,  H01L21/02639 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66287 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848 ,  H01L21/30608

摘要： A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.

公开(公告)号：US10475643B2

公开(公告)日：2019-11-12

申请号：US15876829

申请日：2018-01-22

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Ren-Hua Guo ,  Ju-Ru Hsieh ,  Jen-Hao Yang

IPC分类号： H01L21/31 ,  H01L21/02 ,  C23C16/455 ,  C23C16/458 ,  C23C16/46 ,  C23C16/50 ,  C23C16/52 ,  H01L29/66 ,  C23C16/44 ,  C23C16/509 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/165

摘要： A method for manufacturing a semiconductor device includes introducing a gas into a chamber from a showerhead. The chamber has a sidewall surrounding a pedestal. The temperature of the showerhead is increased. The showerhead is thermally connected to the sidewall of the chamber, and a temperature of the sidewall of the chamber is increased by increasing the temperature of the showerhead.