公开(公告)号：US10957540B2

公开(公告)日：2021-03-23

申请号：US16719311

申请日：2019-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Chin Chen ,  Cheng-Yi Wu ,  Yu-Hung Cheng ,  Ren-Hua Guo ,  Hsiang Liu ,  Chin-Szu Lee

IPC: H01L31/102 ,  H01L21/00 ,  H01L21/20 ,  H01L29/66 ,  H01L29/04 ,  H01L21/02 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165 ,  H01L21/306

Abstract: A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.

公开(公告)号：US10658296B2

公开(公告)日：2020-05-19

申请号：US15282258

申请日：2016-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yi Wu ,  Li-Hsuan Chu ,  Ching-Wen Wen ,  Chia-Chun Hung ,  Chen Liang Chang ,  Chin-Szu Lee ,  Hsiang Liu

IPC: H01L21/00 ,  H01L23/532 ,  H01L27/146 ,  H01L21/02 ,  H01L21/768 ,  H01L21/762 ,  H01L23/48 ,  H01L23/528 ,  H01L23/485

Abstract: A method for semiconductor manufacturing is disclosed. The method includes receiving a device having a first surface through which a first metal or an oxide of the first metal is exposed. The method further includes depositing a dielectric film having Si, N, C, and O over the first surface such that the dielectric film has a higher concentration of N and C in a first portion of the dielectric film near the first surface than in a second portion of the dielectric film further away from the first surface than the first portion. The method further includes forming a conductive feature over the dielectric film. The dielectric film electrically insulates the conductive feature from the first metal or the oxide of the first metal.

公开(公告)号：US20220223528A1

公开(公告)日：2022-07-14

申请号：US17712306

申请日：2022-04-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yi Wu ,  Li-Hsuan Chu ,  Ching-Wen Wen ,  Chia-Chun Hung ,  Chen Liang Chang ,  Chin-Szu Lee ,  Hsiang Liu

IPC: H01L23/532 ,  H01L27/146 ,  H01L21/02 ,  H01L21/768 ,  H01L21/762 ,  H01L23/48 ,  H01L23/528

Abstract: A method for semiconductor manufacturing is disclosed. The method includes receiving a device having a first surface through which a first metal or an oxide of the first metal is exposed. The method further includes depositing a dielectric film having Si, N, C, and O over the first surface such that the dielectric film has a higher concentration of N and C in a first portion of the dielectric film near the first surface than in a second portion of the dielectric film further away from the first surface than the first portion. The method further includes forming a conductive feature over the dielectric film. The dielectric film electrically insulates the conductive feature from the first metal or the oxide of the first metal.

公开(公告)号：US20180350601A1

公开(公告)日：2018-12-06

申请号：US16043286

申请日：2018-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Chin Chen ,  Cheng-Yi Wu ,  Yu-Hung Cheng ,  Ren-Hua Guo ,  Hsiang Liu ,  Chin-Szu Lee

IPC: H01L21/20 ,  H01L29/66 ,  H01L29/04 ,  H01L21/02

Abstract: A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.

公开(公告)号：US11296027B2

公开(公告)日：2022-04-05

申请号：US16681556

申请日：2019-11-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yi Wu ,  Li-Hsuan Chu ,  Ching-Wen Wen ,  Chia-Chun Hung ,  Chen Liang Chang ,  Chin-Szu Lee ,  Hsiang Liu

IPC: H01L23/48 ,  H01L23/532 ,  H01L27/146 ,  H01L21/02 ,  H01L21/768 ,  H01L21/762 ,  H01L23/528 ,  H01L23/485

Abstract: A method for semiconductor manufacturing is disclosed. The method includes receiving a device having a first surface through which a first metal or an oxide of the first metal is exposed. The method further includes depositing a dielectric film having Si, N, C, and O over the first surface such that the dielectric film has a higher concentration of N and C in a first portion of the dielectric film near the first surface than in a second portion of the dielectric film further away from the first surface than the first portion. The method further includes forming a conductive feature over the dielectric film. The dielectric film electrically insulates the conductive feature from the first metal or the oxide of the first metal.

公开(公告)号：US11658032B2

公开(公告)日：2023-05-23

申请号：US17205715

申请日：2021-03-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Chin Chen ,  Cheng-Yi Wu ,  Yu-Hung Cheng ,  Ren-Hua Guo ,  Hsiang Liu ,  Chin-Szu Lee

IPC: H01L29/78 ,  H01L21/331 ,  H01L21/20 ,  H01L29/66 ,  H01L29/04 ,  H01L21/02 ,  H01L29/08 ,  H01L29/165 ,  H01L21/306

CPC classification number: H01L21/2022 ,  H01L21/02002 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/0262 ,  H01L21/02381 ,  H01L21/02502 ,  H01L21/02516 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02636 ,  H01L21/02639 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66287 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848 ,  H01L21/30608

Abstract: A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.

公开(公告)号：US10147609B2

公开(公告)日：2018-12-04

申请号：US15475826

申请日：2017-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Chin Chen ,  Cheng-Yi Wu ,  Yu-Hung Cheng ,  Ren-Hua Guo ,  Hsiang Liu ,  Chin-Szu Lee

IPC: H01L21/336 ,  H01L29/78 ,  H01L21/20 ,  H01L29/66 ,  H01L29/04

Abstract: A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.

公开(公告)号：US20180337128A1

公开(公告)日：2018-11-22

申请号：US16050058

申请日：2018-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yi Wu ,  Li-Hsuan Chu ,  Ching-Wen Wen ,  Chia-Chun Hung ,  Chen Liang Chang ,  Chin-Szu Lee ,  Hsiang Liu

IPC: H01L23/532 ,  H01L27/146 ,  H01L21/02 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/5329 ,  H01L21/0214 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L27/14614 ,  H01L27/1463 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/14687

Abstract: A method for semiconductor manufacturing is disclosed. The method includes receiving a device having a first surface through which a first metal or an oxide of the first metal is exposed. The method further includes depositing a dielectric film having Si, N, C, and O over the first surface such that the dielectric film has a higher concentration of N and C in a first portion of the dielectric film near the first surface than in a second portion of the dielectric film further away from the first surface than the first portion. The method further includes forming a conductive feature over the dielectric film. The dielectric film electrically insulates the conductive feature from the first metal or the oxide of the first metal.

公开(公告)号：US20180175196A1

公开(公告)日：2018-06-21

申请号：US15475826

申请日：2017-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Chin Chen ,  Cheng-Yi Wu ,  Yu-Hung Cheng ,  Ren-Hua Guo ,  Hsiang Liu ,  Chin-Szu Lee

IPC: H01L29/78 ,  H01L29/04 ,  H01L29/06 ,  H01L29/161 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L21/2022 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02516 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/30608 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66287 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.

公开(公告)号：US11901295B2

公开(公告)日：2024-02-13

申请号：US17712306

申请日：2022-04-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yi Wu ,  Li-Hsuan Chu ,  Ching-Wen Wen ,  Chia-Chun Hung ,  Chen Liang Chang ,  Chin-Szu Lee ,  Hsiang Liu

IPC: H01L23/48 ,  H01L23/532 ,  H01L27/146 ,  H01L21/02 ,  H01L21/768 ,  H01L21/762 ,  H01L23/528 ,  H01L23/485

CPC classification number: H01L23/5329 ,  H01L21/0214 ,  H01L21/0228 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02219 ,  H01L21/02271 ,  H01L21/76224 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L27/1463 ,  H01L27/14614 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/14687 ,  H01L21/76831 ,  H01L23/485

Abstract: A method for semiconductor manufacturing is disclosed. The method includes receiving a device having a first surface through which a first metal or an oxide of the first metal is exposed. The method further includes depositing a dielectric film having Si, N, C, and O over the first surface such that the dielectric film has a higher concentration of N and C in a first portion of the dielectric film near the first surface than in a second portion of the dielectric film further away from the first surface than the first portion. The method further includes forming a conductive feature over the dielectric film. The dielectric film electrically insulates the conductive feature from the first metal or the oxide of the first metal.