公开(公告)号：US20230326787A1

公开(公告)日：2023-10-12

申请号：US18336137

申请日：2023-06-16

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Hung Cheng ,  Yu-Chun Chang ,  Ching I Li ,  Ru-Liang Lee

IPC分类号： H01L21/762 ,  H01L27/12

CPC分类号： H01L21/76283 ,  H01L21/76286 ,  H01L27/1203 ,  H01L21/02381

摘要： Deep trench isolation structures for high voltage semiconductor-on-insulator devices are disclosed herein. An exemplary deep trench isolation structure surrounds an active region of a semiconductor-on-insulator substrate. The deep trench isolation structure includes a first insulator sidewall spacer, a second insulator sidewall spacer, and a multilayer silicon-comprising isolation structure disposed between the first insulator sidewall spacer and the second insulator sidewall spacer. The multilayer silicon-comprising isolation structure includes a top polysilicon portion disposed over a bottom silicon portion. The bottom polysilicon portion is formed by a selective deposition process, while the top polysilicon portion is formed by a non-selective deposition process. In some embodiments, the bottom silicon portion is doped with boron.

公开(公告)号：US11264469B2

公开(公告)日：2022-03-01

申请号：US16861478

申请日：2020-04-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Cheng-Ta Wu ,  Chia-Shiung Tsai ,  Jiech-Fun Lu ,  Kuo-Hwa Tzeng ,  Shih-Pei Chou ,  Yu-Hung Cheng ,  Yeur-Luen Tu

IPC分类号： H01L29/40 ,  H01L21/762 ,  H01L21/02 ,  H01L29/06 ,  H01L21/324 ,  H01L21/66 ,  H01L21/311

摘要： Various embodiments of the present application are directed to a method for forming a thin semiconductor-on-insulator (SOI) substrate without implantation radiation and/or plasma damage. In some embodiments, a device layer is epitaxially formed on a sacrificial substrate and an insulator layer is formed on the device layer. The insulator layer may, for example, be formed with a net charge that is negative or neutral. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates. The sacrificial substrate is removed, and the device layer is cyclically thinned until the device layer has a target thickness. Each thinning cycle comprises oxidizing a portion of the device layer and removing oxide resulting from the oxidizing.

公开(公告)号：US20210335861A1

公开(公告)日：2021-10-28

申请号：US17017854

申请日：2020-09-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Hung Cheng ,  Chun-Tsung Kuo ,  Jiech-Fun Lu ,  Min-Ying Tsai ,  Chiao-Chun Hsu ,  Ching I Li

IPC分类号： H01L27/146

摘要： The present disclosure relates to an image sensor having a photodiode surrounded by a back-side deep trench isolation (BDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within an image sensing die and respectively comprises a photodiode configured to convert radiation into an electrical signal. The photodiode comprises a photodiode doping column with a first doping type surrounded by a photodiode doping layer with a second doping type that is different than the first doping type. A BDTI structure is disposed between adjacent pixel regions and extending from the back-side of the image sensing die to a position within the photodiode doping layer. The BDTI structure comprises a doped liner with the second doping type and a dielectric fill layer. The doped liner lines a sidewall surface of the dielectric fill layer.

公开(公告)号：US11069733B2

公开(公告)日：2021-07-20

申请号：US16815371

申请日：2020-03-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Hung Cheng ,  Shyh-Fann Ting ,  Yen-Ting Chiang ,  Yeur-Luen Tu ,  Min-Ying Tsai

IPC分类号： H01L27/146

摘要： In some embodiments, a method is provided. The method includes forming a plurality of trenches in a semiconductor substrate, where the trenches extend into the semiconductor substrate from a back-side of the semiconductor substrate. An epitaxial layer comprising a dopant is formed on lower surfaces of the trenches, sidewalls of the trenches, and the back-side of the semiconductor substrate, where the dopant has a first doping type. The dopant is driven into the semiconductor substrate to form a first doped region having the first doping type along the epitaxial layer, where the first doped region separates a second doped region having a second doping type opposite the first doping type from the sidewalls of the trenches and from the back-side of the semiconductor substrate. A dielectric layer is formed over the back-side of the semiconductor substrate, where the dielectric layer fill the trenches to form back-side deep trench isolation structures.

公开(公告)号：US20210183921A1

公开(公告)日：2021-06-17

申请号：US17187955

申请日：2021-03-01

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Hung Cheng ,  Shyh-Fann Ting ,  Yen-Ting Chiang ,  Yeur-Luen Tu ,  Min-Ying Tsai

IPC分类号： H01L27/146

摘要： In some embodiments, a method is provided. The method includes forming a plurality of trenches in a semiconductor substrate, where the trenches extend into the semiconductor substrate from a back-side of the semiconductor substrate. An epitaxial layer comprising a dopant is formed on lower surfaces of the trenches, sidewalls of the trenches, and the back-side of the semiconductor substrate, where the dopant has a first doping type. The dopant is driven into the semiconductor substrate to form a first doped region having the first doping type along the epitaxial layer, where the first doped region separates a second doped region having a second doping type opposite the first doping type from the sidewalls of the trenches and from the back-side of the semiconductor substrate. A dielectric layer is formed over the back-side of the semiconductor substrate, where the dielectric layer fill the trenches to form back-side deep trench isolation structures.

公开(公告)号：US10658410B2

公开(公告)日：2020-05-19

申请号：US16113066

申请日：2018-08-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Hung Cheng ,  Shyh-Fann Ting ,  Yen-Ting Chiang ,  Yeur-Luen Tu ,  Min-Ying Tsai

IPC分类号： H01L27/146 ,  H04N5/365 ,  H04N5/378

摘要： In some embodiments, a method is provided. The method includes forming a plurality of trenches in a semiconductor substrate, where the trenches extend into the semiconductor substrate from a back-side of the semiconductor substrate. An epitaxial layer comprising a dopant is formed on lower surfaces of the trenches, sidewalls of the trenches, and the back-side of the semiconductor substrate, where the dopant has a first doping type. The dopant is driven into the semiconductor substrate to form a first doped region having the first doping type along the epitaxial layer, where the first doped region separates a second doped region having a second doping type opposite the first doping type from the sidewalls of the trenches and from the back-side of the semiconductor substrate. A dielectric layer is formed over the back-side of the semiconductor substrate, where the dielectric layer fill the trenches to form back-side deep trench isolation structures.

公开(公告)号：US20200006385A1

公开(公告)日：2020-01-02

申请号：US16024962

申请日：2018-07-02

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Min-Ying Tsai ,  Alex Usenko

IPC分类号： H01L27/12 ,  H01L21/02 ,  H01L21/762 ,  H01L21/84 ,  H01L29/04 ,  H01L29/16

摘要： Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate comprising a trap-rich layer with small grain sizes, as well as the resulting SOI substrate. In some embodiments, an amorphous silicon layer is deposited on a high-resistivity substrate. A rapid thermal anneal (RTA) is performed to crystallize the amorphous silicon layer into a trap-rich layer of polysilicon in which a majority of grains are equiaxed. An insulating layer is formed over the trap-rich layer. A device layer is formed over the insulating layer and comprises a semiconductor material. Equiaxed grains are smaller than other grains (e.g., columnar grains). Since a majority of grains in the trap-rich layer are equiaxed, the trap-rich layer has a high grain boundary area and a high density of carrier traps. The high density of carrier traps may, for example, reduce the effects of parasitic surface conduction (PSC).

公开(公告)号：US10395974B1

公开(公告)日：2019-08-27

申请号：US15962214

申请日：2018-04-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Pei Chou ,  Hung-Wen Hsu ,  Jiech-Fun Lu ,  Yu-Hung Cheng ,  Yung-Lung Lin ,  Min-Ying Tsai

IPC分类号： H01L21/762 ,  H01L21/306

摘要： Various embodiments of the present application are directed to a method for forming a thin semiconductor-on-insulator (SOI) substrate at low cost and with low total thickness variation (TTV). In some embodiments, an etch stop layer is epitaxially formed on a sacrificial substrate. A device layer is epitaxially formed on the etch stop layer and has a different crystalline lattice than the etch stop layer. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the etch stop layer are between the sacrificial and handle substrates. The sacrificial substrate is removed. An etch is performed into the etch stop layer to remove the etch stop layer. The etch is performed using an etchant comprising hydrofluoric acid, hydrogen peroxide, and acetic acid.

公开(公告)号：US20180147825A1

公开(公告)日：2018-05-31

申请号：US15613963

申请日：2017-06-05

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chang-Chen Tsao ,  Kuo Liang Lu ,  Ru-Liang Lee ,  Sheng-Hsiang Chuang ,  Yu-Hung Cheng ,  Yeur-Luen Tu ,  Cheng-Kang Hu

IPC分类号： B32B38/10 ,  H01L21/67 ,  H01L21/683 ,  H01L21/68

CPC分类号： B32B38/10 ,  H01L21/67011 ,  H01L21/67092 ,  H01L21/681 ,  H01L21/6835 ,  H01L21/6838

摘要： The present disclosure relates to a method for debonding a pair of bonded substrates. In the method, a debonding apparatus is provided comprising a wafer chuck, a flex wafer assembly, and a set of separating blades. The pair of bonded substrates is placed upon the wafer chuck so that a first substrate of the bonded substrate pair is in contact with a chuck top surface. The flex wafer assembly is placed above the bonded substrate pair so that its first surface is in contact with an upper surface of a second substrate of the bonded substrate pair. A pair of separating blades having different thicknesses is inserted between the first and second substrates from edges of the pair of bonded substrates diametrically opposite to each other while the second substrate is concurrently pulled upward until the flex wafer assembly flexes the second substrate from the first substrate. By providing unbalanced initial torques on opposite sides of the bonded substrate pair, edge defects and wafer breakage are reduced.

公开(公告)号：US09899441B1

公开(公告)日：2018-02-20

申请号：US15337224

申请日：2016-10-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Hung Cheng ,  Cheng-Lung Wu ,  Tung-I Lin ,  Yeur-Luen Tu

IPC分类号： H01L31/0232 ,  H01L27/146

CPC分类号： H01L27/1463 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14645 ,  H01L27/14689 ,  H01L27/14698

摘要： A method for manufacturing a deep trench isolation (DTI) structure with a tri-layer passivation layer is provided. An etch is performed into a semiconductor substrate to form a trench. A first undoped semiconductor layer is formed by epitaxy lining surfaces of the semiconductor substrate that define the trench. A doped semiconductor layer is formed by epitaxy over and lining the first undoped semiconductor layer in the trench. A second undoped semiconductor layer is formed by epitaxy over and lining the doped semiconductor layer in the trench. A structure resulting from the method is also provided.