Invention Application
- Patent Title: ENHANCED MEMORY RELIABILITY IN STACKED MEMORY DEVICES
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Application No.: US16128161Application Date: 2018-09-11
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Publication No.: US20190012232A1Publication Date: 2019-01-10
- Inventor: William C. Plants
- Applicant: Invensas Corporation
- Applicant Address: US CA San Jose
- Assignee: Invensas Corporation
- Current Assignee: Invensas Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: G06F11/10
- IPC: G06F11/10 ; H03M13/29 ; G11C29/00 ; G11C29/44 ; G11C29/42 ; G11C29/52
Abstract:
The invention pertains to semiconductor memories, and more particularly to enhancing the reliability of stacked memory devices. Apparatuses and methods are described for implementing RAID-style error correction to increase the reliability of the stacked memory devices.
Public/Granted literature
- US10409677B2 Enhanced memory reliability in stacked memory devices Public/Granted day:2019-09-10
Information query
