Invention Application
- Patent Title: STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH MULTIPLE THERMAL PATHS AND ASSOCIATED SYSTEMS AND METHODS
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Application No.: US16229257Application Date: 2018-12-21
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Publication No.: US20190122950A1Publication Date: 2019-04-25
- Inventor: Steven K. Groothuis , Jian Li , Haojun Zhang , Paul A. Silvestri , Xiao Li , Shijian Luo , Luke G. England , Brent Keeth , Jaspreet S. Gandhi
- Applicant: Micron Technology, Inc.
- Main IPC: H01L23/36
- IPC: H01L23/36 ; H01L23/367 ; H01L25/00 ; H01L23/373 ; H01L23/42 ; H01L25/065 ; H01L25/18

Abstract:
Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.
Public/Granted literature
- US10741468B2 Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods Public/Granted day:2020-08-11
Information query
IPC分类: