公开(公告)号：US20160351530A1

公开(公告)日：2016-12-01

申请号：US15232525

申请日：2016-08-09

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi ,  Luke G. England ,  Owen R. Fay

IPC: H01L23/00 ,  H01L21/56 ,  H01L25/18 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/81 ,  H01L21/563 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08225 ,  H01L2224/11822 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/14134 ,  H01L2224/1601 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/16505 ,  H01L2224/1701 ,  H01L2224/17181 ,  H01L2224/175 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29309 ,  H01L2224/29311 ,  H01L2224/29316 ,  H01L2224/29324 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29499 ,  H01L2224/3201 ,  H01L2224/32054 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/3301 ,  H01L2224/33505 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/81125 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/81901 ,  H01L2224/81948 ,  H01L2224/83102 ,  H01L2224/83104 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/07811 ,  H01L2924/1461 ,  H01L2924/3841 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/00012

Abstract: Semiconductor devices and device packages include at least one semiconductor die electrically coupled to a substrate through a plurality of conductive structures. The at least one semiconductor die may be a plurality of memory dice, and the substrate may be a logic die. An underfill material disposed between the at least one semiconductor die and the substrate may include a thermally conductive material. An electrically insulating material is disposed between the plurality of conductive structures and the underfill material. Methods of attaching a semiconductor die to a substrate, such as for forming semiconductor device packages, include covering or coating at least an outer side surface of conductive structures, electrically coupling the semiconductor die to the substrate with an electrically insulating material, and disposing a thermally conductive material between the semiconductor die and the substrate.

Abstract translation: 半导体器件和器件封装包括通过多个导电结构电耦合到衬底的至少一个半导体管芯。 所述至少一个半导体管芯可以是多个存储器管芯，并且所述衬底可以是逻辑管芯。 设置在至少一个半导体管芯和衬底之间的底部填充材料可以包括导热材料。 电绝缘材料设置在多个导电结构和底部填充材料之间。 将半导体管芯附着到诸如用于形成半导体器件封装的衬底的方法包括覆盖或涂覆导电结构的至少外侧表面，用电绝缘材料将半导体管芯电耦合到衬底，并且设置热 导电材料在半导体管芯和衬底之间。

公开(公告)号：US20140291834A1

公开(公告)日：2014-10-02

申请号：US13851788

申请日：2013-03-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jaspreet S. Gandhi ,  Luke G. England ,  Owen R. Fay

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L24/81 ,  H01L21/563 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08225 ,  H01L2224/11822 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/14134 ,  H01L2224/1601 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/16505 ,  H01L2224/1701 ,  H01L2224/17181 ,  H01L2224/175 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29309 ,  H01L2224/29311 ,  H01L2224/29316 ,  H01L2224/29324 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29499 ,  H01L2224/3201 ,  H01L2224/32054 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/3301 ,  H01L2224/33505 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/81125 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/81901 ,  H01L2224/81948 ,  H01L2224/83102 ,  H01L2224/83104 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/07811 ,  H01L2924/1461 ,  H01L2924/3841 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/00012

Abstract: Semiconductor devices and device packages include at least one semiconductor die electrically coupled to a substrate through a plurality of conductive structures. The at least one semiconductor die may be a plurality of memory dice, and the substrate may be a logic die. An underfill material disposed between the at least one semiconductor die and the substrate may include a thermally conductive material. An electrically insulating material is disposed between the plurality of conductive structures and the underfill material. Methods of attaching a semiconductor die to a substrate, such as for forming semiconductor device packages, include covering or coating at least an outer side surface of conductive structures, electrically coupling the semiconductor die to the substrate with an electrically insulating material, and disposing a thermally conductive material between the semiconductor die and the substrate.

Abstract translation: 半导体器件和器件封装包括通过多个导电结构电耦合到衬底的至少一个半导体管芯。 所述至少一个半导体管芯可以是多个存储器管芯，并且所述衬底可以是逻辑管芯。 设置在至少一个半导体管芯和衬底之间的底部填充材料可以包括导热材料。 电绝缘材料设置在多个导电结构和底部填充材料之间。 将半导体管芯附着到诸如用于形成半导体器件封装的衬底的方法包括覆盖或涂覆导电结构的至少外侧表面，用电绝缘材料将半导体管芯电耦合到衬底，并且设置热 导电材料在半导体管芯和衬底之间。

公开(公告)号：US20190122950A1

公开(公告)日：2019-04-25

申请号：US16229257

申请日：2018-12-21

Applicant: Micron Technology, Inc.

Inventor： Steven K. Groothuis ,  Jian Li ,  Haojun Zhang ,  Paul A. Silvestri ,  Xiao Li ,  Shijian Luo ,  Luke G. England ,  Brent Keeth ,  Jaspreet S. Gandhi

IPC: H01L23/36 ,  H01L23/367 ,  H01L25/00 ,  H01L23/373 ,  H01L23/42 ,  H01L25/065 ,  H01L25/18

Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.

公开(公告)号：US20170207139A1

公开(公告)日：2017-07-20

申请号：US15478133

申请日：2017-04-03

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Kyle K. Kirby ,  Luke G. England ,  Jaspreet S. Gandhi

IPC: H01L21/66 ,  H01L23/00

CPC classification number: H01L22/32 ,  H01L22/14 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02163 ,  H01L2224/0391 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/00012 ,  H01L2924/206 ,  H01L2924/01047 ,  H01L2924/00 ,  H01L2224/05552

Abstract: An interconnect assembly includes a bond pad and an interconnect structure configured to electrically couple an electronic structure to the bond pad. The interconnect structure physically contacts areas of the bond pad that are located outside of a probe contact area that may have been damaged during testing. Insulating material covers the probe contact area and defines openings spaced apart from the probe contact area. The interconnect structure extends through the openings to contact the bond pad.

公开(公告)号：US20140353815A1

公开(公告)日：2014-12-04

申请号：US14464410

申请日：2014-08-20

Applicant: Micron Technology, Inc.

Inventor： Luke G. England ,  Paul A. Silvestri ,  Michel Koopmans

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/367 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/561 ,  H01L21/6836 ,  H01L22/10 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/05655 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/00

Abstract: Methods of fabricating multi-die assemblies including a wafer segment having no integrated circuitry thereon and having a plurality of vertically stacked dice thereon electrically interconnected by conductive through vias, resulting multi-die assemblies, and semiconductor devices comprising such multi-die assemblies. The wafer segment may function as a heat sink to enhance heat transfer from the stacked dice in the resulting multi-die assembly. The die stacks are fabricated at the wafer level on a base wafer, from which the wafer segment and die stacks are singulated after at least peripheral encapsulation.

Abstract translation: 制造多模组件的方法，其包括在其上没有集成电路并且具有多个垂直堆叠的骰子的晶片片段，其上通过导电通孔，所得到的多骰子组件和包括这种多模组件的半导体器件电连接。 晶片段可以用作散热器，以增强在所得到的多模组件中从堆叠的骰子的热传递。 芯片堆叠在基底晶片上的晶片级制造，晶片段和管芯堆叠至少在至少外围封装之后被分割。

公开(公告)号：US20140017823A1

公开(公告)日：2014-01-16

申请号：US14029187

申请日：2013-09-17

Applicant: Micron Technology, Inc.

Inventor： Luke G. England ,  Paul A. Silvestri ,  Michel Koopmans

IPC: H01L21/56 ,  H01L21/66

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/561 ,  H01L21/6836 ,  H01L22/10 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/05655 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/00

Abstract: Methods of fabricating multi-die assemblies including a wafer segment having no integrated circuitry thereon and having a plurality of vertically stacked dice thereon electrically interconnected by conductive through vias, resulting multi-die assemblies, and semiconductor devices comprising such multi-die assemblies. The wafer segment may function as a heat sink to enhance heat transfer from the stacked dice in the resulting multi-die assembly. The die stacks are fabricated at the wafer level on a base wafer, from which the wafer segment and die stacks are singulated after at least peripheral encapsulation.

Abstract translation: 制造多模组件的方法，其包括在其上没有集成电路并且具有多个垂直堆叠的骰子的晶片片段，其上通过导电通孔，所得到的多骰子组件和包括这种多模组件的半导体器件电连接。 晶片段可以用作散热器，以增强在所得到的多模组件中从堆叠的骰子的热传递。 芯片堆叠在基底晶片上的晶片级制造，晶片段和管芯堆叠至少在至少外围封装之后被分割。

公开(公告)号：US20200350224A1

公开(公告)日：2020-11-05

申请号：US16936639

申请日：2020-07-23

Applicant: Micron Technology, Inc.

Inventor： Steven K. Groothuis ,  Jian Li ,  Haojun Zhang ,  Paul A. Silvestri ,  Xiao Li ,  Shijian Luo ,  Luke G. England ,  Brent Keeth ,  Jaspreet S. Gandhi

IPC: H01L23/36 ,  H01L25/00 ,  H01L23/367 ,  H01L25/065 ,  H01L25/18 ,  H01L23/373 ,  H01L23/42

Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.

公开(公告)号：US10741460B2

公开(公告)日：2020-08-11

申请号：US16162195

申请日：2018-10-16

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Kyle K. Kirby ,  Luke G. England ,  Jaspreet S. Gandhi

IPC: H01L21/66 ,  H01L23/00

Abstract: An interconnect assembly includes a bond pad and an interconnect structure configured to electrically couple an electronic structure to the bond pad. The interconnect structure physically contacts areas of the bond pad that are located outside of a probe contact area that may have been damaged during testing. Insulating material covers the probe contact area and defines openings spaced apart from the probe contact area. The interconnect structure extends through the openings to contact the bond pad.

公开(公告)号：US20190051569A1

公开(公告)日：2019-02-14

申请号：US16162195

申请日：2018-10-16

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Kyle K. Kirby ,  Luke G. England ,  Jaspreet S. Gandhi

IPC: H01L21/66 ,  H01L23/00

Abstract: An interconnect assembly includes a bond pad and an interconnect structure configured to electrically couple an electronic structure to the bond pad. The interconnect structure physically contacts areas of the bond pad that are located outside of a probe contact area that may have been damaged during testing. Insulating material covers the probe contact area and defines openings spaced apart from the probe contact area. The interconnect structure extends through the openings to contact the bond pad.

公开(公告)号：US09379091B2

公开(公告)日：2016-06-28

申请号：US14464410

申请日：2014-08-20

Applicant: Micron Technology, Inc.

Inventor： Luke G. England ,  Paul A. Silvestri ,  Michel Koopmans

IPC: H01L23/02 ,  H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L21/683 ,  H01L23/367 ,  H01L23/48 ,  H01L23/31 ,  H01L21/66 ,  H01L25/18 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/561 ,  H01L21/6836 ,  H01L22/10 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/05655 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/00

Abstract: Methods of fabricating multi-die assemblies including a wafer segment having no integrated circuitry thereon and having a plurality of vertically stacked dice thereon electrically interconnected by conductive through vias, resulting multi-die assemblies, and semiconductor devices comprising such multi-die assemblies. The wafer segment may function as a heat sink to enhance heat transfer from the stacked dice in the resulting multi-die assembly. The die stacks are fabricated at the wafer level on a base wafer, from which the wafer segment and die stacks are singulated after at least peripheral encapsulation.

Abstract translation: 制造多模组件的方法，其包括在其上没有集成电路并且具有多个垂直堆叠的骰子的晶片片段，其上通过导电通孔，所得到的多骰子组件和包括这种多模组件的半导体器件电连接。 晶片段可以用作散热器，以增强在所得到的多模组件中从堆叠的骰子的热传递。 芯片堆叠在基底晶片上的晶片级制造，晶片段和管芯堆叠至少在至少外围封装之后被分割。