发明申请
- 专利标题: VIA BLOCKING LAYER
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申请号: US16302692申请日: 2016-06-22
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公开(公告)号: US20190122982A1公开(公告)日: 2019-04-25
- 发明人: Rami Hourani , Marie Krysak , Florian Gstrein , Ruth A. Brain , Mark T. Bohr , Manish Chandhok
- 申请人: Intel Corporation
- 国际申请: PCT/US2016/038686 WO 20160622
- 主分类号: H01L23/522
- IPC分类号: H01L23/522 ; H01L21/762 ; H01L21/768 ; H01L21/8234 ; H01L21/02
摘要:
An embodiment includes an apparatus comprising: a metal layer comprising a plurality of interconnect lines on a plurality of vias; an additional metal layer comprising first, second, and third interconnect lines on first, second, and third vias; the first and third vias coupling the first and third interconnect lines to two of the plurality of interconnect lines; a lateral interconnect, included entirely within the additional metal layer, directly connected to each of the first, second, and third interconnect lines; and an insulator layer included entirely between two sidewalls of the second via. Other embodiments are described herein.
公开/授权文献
- US10535601B2 Via blocking layer 公开/授权日:2020-01-14
信息查询
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