Invention Application
- Patent Title: ASYMMETRIC HIGH-K DIELECTRIC FOR REDUCING GATE INDUCED DRAIN LEAKAGE
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Application No.: US16440106Application Date: 2019-06-13
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Publication No.: US20190296120A1Publication Date: 2019-09-26
- Inventor: Anthony I. CHOU , Arvind Kumar , Chung-Hsun Lin , Shreesh Narasimha , Claude Ortolland , Jonathan T. Shaw
- Applicant: International Business Machines Corporation
- Main IPC: H01L29/423
- IPC: H01L29/423 ; H01L21/02 ; H01L21/28 ; H01L21/8234 ; H01L21/426 ; H01L21/84 ; H01L21/324 ; H01L29/51 ; H01L21/3115 ; H01L29/40 ; H01L21/265 ; H01L29/66 ; H01L29/78 ; H01L29/417 ; H01L21/283 ; H01L21/3065 ; H01L21/308

Abstract:
An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
Public/Granted literature
- US10734492B2 Asymmetric high-k dielectric for reducing gate induced drain leakage Public/Granted day:2020-08-04
Information query
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