Invention Application
- Patent Title: CHANNEL LAYER FORMATION FOR III-V METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTORS (MOSFETS)
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Application No.: US16024694Application Date: 2018-06-29
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Publication No.: US20200006069A1Publication Date: 2020-01-02
- Inventor: Gilbert DEWEY , Matthew METZ , Willy RACHMADY , Sean MA , Nicholas MINUTILLO , Cheng-Ying HUANG , Tahir GHANI , Jack KAVALIEROS , Anand MURTHY , Harold KENNEL
- Applicant: Intel Corporation
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L29/20 ; H01L29/04 ; H01L27/12 ; H01L29/78

Abstract:
Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device including a substrate and an insulator layer above the substrate. A channel area may include an III-V material relaxed grown on the insulator layer. A source area may be above the insulator layer, in contact with the insulator layer, and adjacent to a first end of the channel area. A drain area may be above the insulator layer, in contact with the insulator layer, and adjacent to a second end of the channel area that is opposite to the first end of the channel area. The source area or the drain area may include one or more seed components including a seed material with free surface. Other embodiments may be described and/or claimed.
Public/Granted literature
- US11508577B2 Channel layer formation for III-V metal-oxide-semiconductor field effect transistors (MOSFETs) Public/Granted day:2022-11-22
Information query
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