公开(公告)号：US20200006576A1

公开(公告)日：2020-01-02

申请号：US16024701

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Sean MA ,  Nicholas MINUTILLO ,  Cheng-Ying HUANG ,  Tahir GHANI ,  Jack KAVALIEROS ,  Anand MURTHY ,  Harold KENNEL ,  Gilbert DEWEY ,  Matthew METZ ,  Willy RACHMADY

IPC: H01L29/786 ,  H01L29/205 ,  H01L29/423 ,  H01L29/04 ,  H01L29/66

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. A semiconductor device may include isolation areas above a substrate to form a trench between the isolation areas. A first buffer layer is over the substrate, in contact with the substrate, and within the trench. A second buffer layer is within the trench over the first buffer layer, and in contact with the first buffer layer. A channel area is above the first buffer layer, above a portion of the second buffer layer that are below a source area or a drain area, and without being vertically above a portion of the second buffer layer. In addition, the source area or the drain area is above the second buffer layer, in contact with the second buffer layer, and adjacent to the channel area. Other embodiments may be described and/or claimed.

公开(公告)号：US20200006069A1

公开(公告)日：2020-01-02

申请号：US16024694

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Matthew METZ ,  Willy RACHMADY ,  Sean MA ,  Nicholas MINUTILLO ,  Cheng-Ying HUANG ,  Tahir GHANI ,  Jack KAVALIEROS ,  Anand MURTHY ,  Harold KENNEL

IPC: H01L21/02 ,  H01L29/20 ,  H01L29/04 ,  H01L27/12 ,  H01L29/78

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device including a substrate and an insulator layer above the substrate. A channel area may include an III-V material relaxed grown on the insulator layer. A source area may be above the insulator layer, in contact with the insulator layer, and adjacent to a first end of the channel area. A drain area may be above the insulator layer, in contact with the insulator layer, and adjacent to a second end of the channel area that is opposite to the first end of the channel area. The source area or the drain area may include one or more seed components including a seed material with free surface. Other embodiments may be described and/or claimed.

公开(公告)号：US20200006492A1

公开(公告)日：2020-01-02

申请号：US16022510

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Siddharth CHOUKSEY ,  Glenn GLASS ,  Anand MURTHY ,  Harold KENNEL ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Ashish AGRAWAL ,  Seung Hoon SUNG

IPC: H01L29/165 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.

公开(公告)号：US20150200301A1

公开(公告)日：2015-07-16

申请号：US14667544

申请日：2015-03-24

Applicant: Intel Corporation

Inventor： Jacob Jensen ,  Tahir GHANI ,  Mark Y. LIU ,  Harold KENNEL ,  Robert JAMES

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/417 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L21/268 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A non-planar transistor including partially melted raised semiconductor source/drains disposed on opposite ends of a semiconductor fin with the gate stack disposed there between. The raised semiconductor source/drains comprise a super-activated dopant region above a melt depth and an activated dopant region below the melt depth. The super-activated dopant region has a higher activated dopant concentration than the activated dopant region and/or has an activated dopant concentration that is constant throughout the melt region. A fin is formed on a substrate and a semiconductor material or a semiconductor material stack is deposited on regions of the fin disposed on opposite sides of a channel region to form raised source/drains. A pulsed laser anneal is performed to melt only a portion of the deposited semiconductor material above a melt depth.

Abstract translation: 一种非平面晶体管，其包括设置在半导体鳍片的相对端上的部分熔融的凸起半导体源极/漏极，其间设置有栅极堆叠。 升高的半导体源极/漏极包括在熔体深度之上的超激活掺杂剂区域和低于熔体深度的活化掺杂剂区域。 超活化掺杂剂区域具有比活化的掺杂剂区域更高的活化掺杂剂浓度和/或具有在整个熔融区域中恒定的活化的掺杂剂浓度。 翅片形成在基板上，并且半导体材料或半导体材料堆叠沉积在设置在沟道区域的相对侧上的翅片的区域上以形成升高的源极/漏极。 进行脉冲激光退火以仅将融化的半导体材料的一部分熔化在熔体深度之上。

公开(公告)号：US20230006065A1

公开(公告)日：2023-01-05

申请号：US17899429

申请日：2022-08-30

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Willy RACHMADY ,  Jack T. KAVALIEROS ,  Cheng-Ying HUANG ,  Matthew V. METZ ,  Sean T. MA ,  Harold KENNEL ,  Tahir GHANI

IPC: H01L29/78 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28

Abstract: Techniques are disclosed for an integrated circuit including a ferroelectric gate stack including a ferroelectric layer, an interfacial oxide layer, and a gate electrode. The ferroelectric layer can be voltage activated to switch between two ferroelectric states. Employing such a ferroelectric layer provides a reduction in leakage current in an off-state and provides an increase in charge in an on-state. The interfacial oxide layer can be formed between the ferroelectric layer and the gate electrode. Alternatively, the ferroelectric layer can be formed between the interfacial oxide layer and the gate electrode.

公开(公告)号：US20200098874A1

公开(公告)日：2020-03-26

申请号：US16141301

申请日：2018-09-25

Applicant: Intel Corporation

Inventor： Justin WEBER ,  Harold KENNEL ,  Abhishek SHARMA ,  Christopher JEZEWSKI ,  Matthew V. METZ ,  Tahir GHANI ,  Jack T. KAVALIEROS ,  Benjamin CHU-KUNG ,  Van H. LE ,  Arnab SEN GUPTA

IPC: H01L29/36 ,  H01L29/22 ,  H01L29/24 ,  H01L29/47 ,  H01L29/267 ,  H01L29/45 ,  H01L21/02 ,  H01L21/768 ,  H01L21/322

Abstract: Embodiments herein describe techniques for an integrated circuit that includes a substrate, a semiconductor device on the substrate, and a contact stack above the substrate and coupled to the semiconductor device. The contact stack includes a contact metal layer, and a semiconducting oxide layer adjacent to the contact metal layer. The semiconducting oxide layer includes a semiconducting oxide material, while the contact metal layer includes a metal with a sufficient Schottky-barrier height to induce an interfacial electric field between the semiconducting oxide layer and the contact metal layer to reject interstitial hydrogen from entering the semiconductor device through the contact stack. Other embodiments may be described and/or claimed.

公开(公告)号：US20240006489A1

公开(公告)日：2024-01-04

申请号：US18367843

申请日：2023-09-13

Applicant: Intel Corporation

Inventor： Aaron LILAK ,  Rishabh MEHANDRU ,  Willy RACHMADY ,  Harold KENNEL ,  Tahir GHANI

IPC: H01L29/08 ,  H01L21/02 ,  H01L21/8238

CPC classification number: H01L29/0847 ,  H01L21/02356 ,  H01L21/02592 ,  H01L21/823871 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823807

Abstract: A device is disclosed. The device includes a channel, a first source-drain region adjacent a first portion of the channel, the first source-drain region including a first crystalline portion that includes a first region of metastable dopants, a second source-drain region adjacent a second portion of the channel, the second source-drain region including a second crystalline portion that includes a second region of metastable dopants. A gate conductor is on the channel.

公开(公告)号：US20220406895A1

公开(公告)日：2022-12-22

申请号：US17869622

申请日：2022-07-20

Applicant: Intel Corporation

Inventor： Siddharth CHOUKSEY ,  Glenn GLASS ,  Anand MURTHY ,  Harold KENNEL ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Ashish AGRAWAL ,  Seung Hoon SUNG

IPC: H01L29/165 ,  H01L21/8234 ,  H01L29/06 ,  H01L27/088

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.

公开(公告)号：US20220140076A1

公开(公告)日：2022-05-05

申请号：US17576765

申请日：2022-01-14

Applicant: Intel Corporation

Inventor： Cheng-Ying HUANG ,  Tahir GHANI ,  Jack KAVALIEROS ,  Anand MURTHY ,  Harold KENNEL ,  Gilbert DEWEY ,  Matthew METZ ,  Willy RACHMADY ,  Sean MA ,  Nicholas MINUTILLO

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/205 ,  H01L29/417 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device having a channel area including a channel III-V material, and a source area including a first portion and a second portion of the source area. The first portion of the source area includes a first III-V material, and the second portion of the source area includes a second III-V material. The channel III-V material, the first III-V material and the second III-V material may have a same lattice constant. Moreover, the first III-V material has a first bandgap, and the second III-V material has a second bandgap, the channel III-V material has a channel III-V material bandgap, where the channel material bandgap, the second bandgap, and the first bandgap form a monotonic sequence of bandgaps. Other embodiments may be described and/or claimed.

公开(公告)号：US20190393249A1

公开(公告)日：2019-12-26

申请号：US16016387

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Aaron LILAK ,  Justin WEBER ,  Harold KENNEL ,  Willy RACHMADY ,  Gilbert DEWEY ,  Van H. LE ,  Abhishek SHARMA ,  Patrick MORROW

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/78 ,  H01L21/8256

Abstract: Embodiments herein describe techniques for a semiconductor device including a first transistor above a substrate, an insulator layer above the first transistor, and a second transistor above the insulator layer. The first transistor includes a first channel layer above the substrate, and a first gate electrode above the first channel layer. The insulator layer is next to a first source electrode of the first transistor above the first channel layer, next to a first drain electrode of the first transistor above the first channel layer, and above the first gate electrode. The second transistor includes a second channel layer above the insulator layer, and a second gate electrode separated from the second channel layer by a gate dielectric layer. Other embodiments may be described and/or claimed.