Invention Application
- Patent Title: CHANNEL LAYER FOR III-V METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTORS (MOSFETS)
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Application No.: US16024699Application Date: 2018-06-29
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Publication No.: US20200006523A1Publication Date: 2020-01-02
- Inventor: Matthew METZ , Willy RACHMADY , Sean MA , Jessica TORRES , Nicholas MINUTILLO , Cheng-Ying HUANG , Anand MURTHY , Harold KENNEL , Gilbert DEWEY , Jack KAVALIEROS , Tahir GHANI
- Applicant: Intel Corporation
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/02

Abstract:
Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device including a substrate with a surface that is substantially flat. A channel area including an III-V compound may be above the substrate, where the channel area is an epitaxial layer directly in contact with the surface of the substrate. A gate dielectric layer is adjacent to the channel area and in direct contact with the channel area, while a gate electrode is adjacent to the gate dielectric layer. Other embodiments may be described and/or claimed.
Information query
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