Invention Application
- Patent Title: ISOLATION SCHEMES FOR GATE-ALL-AROUND TRANSISTOR DEVICES
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Application No.: US16024046Application Date: 2018-06-29
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Publication No.: US20200006559A1Publication Date: 2020-01-02
- Inventor: RISHABH MEHANDRU , STEPHEN M. CEA , BISWAJEET GUHA , TAHIR GHANI , WILLIAM HSU
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/762 ; H01L21/761 ; H01L29/06 ; H01L29/66 ; H01L29/423

Abstract:
Isolation schemes for gate-all-around (GAA) transistor devices are provided herein. In some cases, the isolation schemes include changing the semiconductor nanowires/nanoribbons in a targeted channel region between active or functional transistor devices to electrically isolate those active devices. The targeted channel region is referred to herein as a dummy channel region, as it is not used as an actual channel region for an active or functional transistor device. The semiconductor nanowires/nanoribbons in the dummy channel region can be changed by converting them to an electrical insulator and/or by adding dopant that is opposite in type relative to surrounding source/drain material (to create a p-n junction). The isolation schemes described herein enable neighboring active devices to retain strain in the nanowires/nanoribbons of their channel regions, thereby improving device performance.
Public/Granted literature
- US11335807B2 Isolation schemes for gate-all-around transistor devices Public/Granted day:2022-05-17
Information query
IPC分类: