公开(公告)号：US20200006559A1

公开(公告)日：2020-01-02

申请号：US16024046

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： RISHABH MEHANDRU ,  STEPHEN M. CEA ,  BISWAJEET GUHA ,  TAHIR GHANI ,  WILLIAM HSU

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/761 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423

Abstract: Isolation schemes for gate-all-around (GAA) transistor devices are provided herein. In some cases, the isolation schemes include changing the semiconductor nanowires/nanoribbons in a targeted channel region between active or functional transistor devices to electrically isolate those active devices. The targeted channel region is referred to herein as a dummy channel region, as it is not used as an actual channel region for an active or functional transistor device. The semiconductor nanowires/nanoribbons in the dummy channel region can be changed by converting them to an electrical insulator and/or by adding dopant that is opposite in type relative to surrounding source/drain material (to create a p-n junction). The isolation schemes described herein enable neighboring active devices to retain strain in the nanowires/nanoribbons of their channel regions, thereby improving device performance.

公开(公告)号：US20200006488A1

公开(公告)日：2020-01-02

申请号：US16020361

申请日：2018-06-27

Applicant: INTEL CORPORATION

Inventor： RISHABH MEHANDRU ,  BISWAJEET GUHA ,  ANUPAMA BOWONDER ,  ANAND S. MURTHY ,  TAHIR GHANI ,  STEPHEN M. CEA

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78 ,  H01L21/74 ,  H01L29/66

Abstract: Integrated circuit structures including a buried etch-stop layer to help control transistor source/drain depth are provided herein. The buried etch-stop layer addresses the issue of the source/drain etch (or epi-undercut (EUC) etch) going below the bottom of the active height of the channel region, as such an issue can result in un-controlled sub-fin leakage that causes power consumption degradation and other undesired performance issues. The buried etch-stop layer is formed below the channel material, such as in the epitaxial stack that includes the channel material, and acts to slow the removal of material after the channel material has been removed when etching to form the source/drain trenches. In other words, the buried etch-stop layer includes different material from the channel material that can be etched, for at least one given etchant, at a relatively slower rate than the channel material to help control the source/drain trench depth.

公开(公告)号：US20200006525A1

公开(公告)日：2020-01-02

申请号：US16023024

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： DAX M. CRUM ,  BISWAJEET GUHA ,  WILLIAM HSU ,  STEPHEN M. CEA ,  TAHIR GHANI

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/423 ,  H01L21/02

Abstract: Integrated circuit structures including increased transistor source/drain (S/D) contact area using a sacrificial S/D layer are provided herein. The sacrificial layer, which includes different material from the S/D material, is deposited into the S/D trenches prior to the epitaxial growth of that S/D material, such that the sacrificial layer acts as a space-holder below the S/D material. During S/D contact processing, the sacrificial layer can be selectively etched relative to the S/D material to at least partially remove it, leaving space below the S/D material for the contact metal to fill. In some cases, the contact metal is also between portions of the S/D material. In some cases, the contact metal wraps around the epi S/D, such as when dielectric wall structures on either side of the S/D region are employed. By increasing the S/D contact area, the contact resistance is reduced, thereby improving the performance of the transistor device.