公开(公告)号：US20200381549A1

公开(公告)日：2020-12-03

申请号：US16998382

申请日：2020-08-20

Applicant: INTEL CORPORATION

Inventor： STEPHEN M. CEA ,  ROZA KOTLYAR ,  HAROLD W. KENNEL ,  GLENN A. GLASS ,  ANAND S. MURTHY ,  WILLY RACHMADY ,  TAHIR GHANI

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L27/092 ,  H01L29/04 ,  H01L29/06 ,  H01L29/161

Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based NMOS transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, a germanium or silicon germanium film is cladded onto silicon fins in order to provide a desired tensile strain in the core of the fin, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and cladding deposition can occur at a plurality of locations within typical process flow. In various embodiments, fins may be formed with a minimum width (or later thinned) so as to improve transistor performance. In some embodiments, a thinned fin also increases tensile strain across the core of a cladded fin. In some cases, strain in the core may be further enhanced by adding an embedded silicon epitaxial source and drain.

公开(公告)号：US20190259835A1

公开(公告)日：2019-08-22

申请号：US16402739

申请日：2019-05-03

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  TAHIR GHANI

IPC: H01L29/06 ,  H01L29/423 ,  H01L21/285 ,  H01L29/66 ,  H01L29/08 ,  H01L21/768 ,  H01L21/3215 ,  H01L27/092 ,  H01L29/417 ,  H01L23/535 ,  H01L29/78 ,  H01L29/45 ,  H01L29/36 ,  H01L21/02 ,  H01L29/167 ,  H01L29/49 ,  H01L29/165 ,  H01L29/778

Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

公开(公告)号：US20190049514A1

公开(公告)日：2019-02-14

申请号：US16073688

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： KEVIN P. O'BRIEN ,  KAAN OGUZ ,  CHRISTOPHER J. WIEGAND ,  MARK L. DOCZY ,  BRIAN S. DOYLE ,  MD TOFIZUR RAHMAN ,  OLEG GOLONZKA ,  TAHIR GHANI

IPC: G01R31/28 ,  G01R31/315 ,  H01L21/66 ,  G01R33/09 ,  H01L43/12

CPC classification number: G01R31/2831 ,  G01N24/10 ,  G01R31/315 ,  G01R33/098 ,  G01R33/60 ,  G01R35/00 ,  H01L22/14 ,  H01L43/12

Abstract: Techniques are disclosed for carrying out ferromagnetic resonance (FMR) testing on whole wafers populated with one or more buried magnetic layers. The techniques can be used to verify or troubleshoot processes for forming the buried magnetic layers, without requiring the wafer to be broken. The techniques can also be used to distinguish one magnetic layer from others in the same stack, based on a unique frequency response of that layer. One example methodology includes moving a wafer proximate to a waveguide (within 500 microns, but without shorting), energizing a DC magnetic field near the target measurement point, applying an RF input signal through the waveguide, collecting resonance spectra of the frequency response of the waveguide, and decomposing the resonance spectra into magnetic properties of the target layer. One or both of the DC magnetic field and RF input signal can be swept to generate a robust set of resonance spectra.

公开(公告)号：US20180358440A1

公开(公告)日：2018-12-13

申请号：US15778863

申请日：2015-12-24

Applicant: INTEL CORPORATION

Inventor： CHANDRA S. MOHAPATRA ,  GLENN A. GLASS ,  ANAND S. MURTHY ,  KARTHIK JAMBUNATHAN ,  WILLY RACHMADY ,  GILBERT DEWEY ,  TAHIR GHANI ,  JACK T. KAVALIEROS

IPC: H01L29/10 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/1054 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/42392 ,  H01L29/66356 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7391 ,  H01L29/785 ,  H01L29/78696

Abstract: Techniques are disclosed for forming transistor structures including tensile-strained germanium (Ge) channel material. The transistor structures may be used for either or both of n-type and p-type transistor devices, as tensile-strained Ge has very high carrier mobility properties suitable for both types. Thus, a simplified CMOS integration scheme may be achieved by forming n-MOS and p-MOS devices included in the CMOS device using the techniques described herein. In some cases, the tensile-strained Ge may be achieved by epitaxially growing the Ge material on a group III-V material having a lattice constant that is higher than that of Ge and/or by applying a macroscopic 3-point bending to the die on which the transistor is formed. The techniques may be used to form transistors having planar or non-planar configurations, such as finned configurations (e.g., finFET or tri-gate) or gate-all-around (GAA) configurations (including at least one nanowire).

公开(公告)号：US20180247939A1

公开(公告)日：2018-08-30

申请号：US15754871

申请日：2015-09-25

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  PRASHANT MAJHI ,  ANAND S. MURTHY ,  TAHIR GHANI ,  DANIEL B. AUBERTINE ,  HEIDI M. MEYER ,  KARTHIK JAMBUNATHAN ,  GOPINATH BHIMARASETTI

IPC: H01L27/092 ,  H01L29/10 ,  H01L29/08 ,  H01L29/36 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/762 ,  H01L29/423 ,  H01L21/02

CPC classification number: H01L27/0924 ,  B82Y10/00 ,  H01L21/02238 ,  H01L21/2252 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/324 ,  H01L21/76205 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1079 ,  H01L29/36 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: Techniques are disclosed for controlling transistor sub-fin leakage. The techniques can be used for highly scaled finFETs, as well as other non-planar transistors. In some cases, the techniques include exposing a middle portion of a fin structure formed on a substrate and then converting the exposed portion to an electrically isolating material via a doping or oxidation process. For example, a monolayer doping (MLD) process may be used to deliver dopants to the exposed portion of the fin in a self-saturated monolayer scheme. In another example case, thermal oxidation may be used to convert the exposed portion to an insulator material. In some cases, a barrier layer (e.g., including carbon doping) may be located above the exposed portion of the fin to help prevent the doping or oxidation process from affecting the upper region of the fin, which is used for the transistor channel.

公开(公告)号：US20180019170A1

公开(公告)日：2018-01-18

申请号：US15668288

申请日：2017-08-03

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  DANIEL B. AUBERTINE ,  ANAND S. MURTHY ,  GAURAV THAREJA ,  TAHIR GHANI

IPC: H01L21/8238 ,  H01L29/10

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/8258 ,  H01L29/1054

Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom semiconductor material of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type material. The p-type material can be completely independent of the process for the n-type material, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.

公开(公告)号：US20170330966A1

公开(公告)日：2017-11-16

申请号：US15525183

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： KARTHIK JAMBUNATHAN ,  GLENN A. GLASS ,  CHANDRA S. MOHAPATRA ,  ANAND S. MURTHY ,  STEPHEN M. CEA ,  TAHIR GHANI

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7831 ,  H01L29/0607 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

Abstract: An embodiment includes an apparatus comprising: a fin structure on a substrate, the fin structure including fin top and bottom portions, a channel including a majority carrier, and an epitaxial (EPI) layer; an insulation layer including insulation layer top and bottom portions adjacent the fin top and bottom portions; wherein (a) the EPI layer comprises one or more of group IV and III-V materials, (b) the fin bottom portion includes a fin bottom portion concentration of dopants of opposite polarity to the majority carrier, (c) the fin top portion includes a fin top portion concentration of the dopants less than the fin bottom portion concentration, (d) the insulation layer bottom portion includes an insulation layer bottom portion concentration of the dopants, and (e) the insulation layer top portion includes an insulation top layer portion concentration greater than the insulation bottom portion concentration. Other embodiments are described herein.

公开(公告)号：US20160027781A1

公开(公告)日：2016-01-28

申请号：US14875167

申请日：2015-10-05

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  TAHIR GHANI

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/267

CPC classification number: H01L29/78618 ,  H01L21/76805 ,  H01L21/76886 ,  H01L21/76895 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/267 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. In some example embodiments, the techniques can be used to implement the contacts of MOS transistors of a CMOS device, where an intermediate III-V semiconductor material layer is provided between the p-type and n-type source/drain regions and their respective contact metals to significantly reduce contact resistance. The intermediate III-V semiconductor material layer may have a small bandgap (e.g., lower than 0.5 eV) and/or otherwise be doped to provide the desired conductivity. The techniques can be used on numerous transistor architectures (e.g., planar, finned, and nanowire transistors), including strained and unstrained channel structures.

公开(公告)号：US20220157820A1

公开(公告)日：2022-05-19

申请号：US17588938

申请日：2022-01-31

Applicant: Intel Corporation

Inventor： ABHISHEK A. SHARMA ,  VAN H. LE ,  GILBERT DEWEY ,  SHRIRAM SHIVARAMAN ,  YIH WANG ,  TAHIR GHANI ,  JACK T. KAVALIEROS

IPC: H01L27/108 ,  H01L29/417 ,  H01L29/45 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786

Abstract: Embodiments herein describe techniques for a semiconductor device including a TFT having a gate electrode with a gate length determined by a spacer. Embodiments may include a gate electrode above a substrate, a channel layer above the gate electrode, and a source electrode, a drain electrode, and a spacer above the channel layer. The drain electrode may be separated from the source electrode by the spacer. The drain electrode and the source electrode may have different widths or include different materials. Furthermore, the spacer may overlap with the gate electrode, hence the gate length of the gate electrode may be determined by the spacer width. Other embodiments may be described and/or claimed.

公开(公告)号：US20200006525A1

公开(公告)日：2020-01-02

申请号：US16023024

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： DAX M. CRUM ,  BISWAJEET GUHA ,  WILLIAM HSU ,  STEPHEN M. CEA ,  TAHIR GHANI

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/423 ,  H01L21/02

Abstract: Integrated circuit structures including increased transistor source/drain (S/D) contact area using a sacrificial S/D layer are provided herein. The sacrificial layer, which includes different material from the S/D material, is deposited into the S/D trenches prior to the epitaxial growth of that S/D material, such that the sacrificial layer acts as a space-holder below the S/D material. During S/D contact processing, the sacrificial layer can be selectively etched relative to the S/D material to at least partially remove it, leaving space below the S/D material for the contact metal to fill. In some cases, the contact metal is also between portions of the S/D material. In some cases, the contact metal wraps around the epi S/D, such as when dielectric wall structures on either side of the S/D region are employed. By increasing the S/D contact area, the contact resistance is reduced, thereby improving the performance of the transistor device.