公开(公告)号：US20200006340A1

公开(公告)日：2020-01-02

申请号：US16024064

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： AARON D. LILAK ,  RISHABH MEHANDRU ,  ANH PHAN ,  GILBERT DEWEY ,  WILLY RACHMADY ,  STEPHEN M. CEA ,  SAYED HASAN ,  KERRYANN M. FOLEY ,  PATRICK MORROW ,  COLIN D. LANDON ,  EHREN MANNEBACH

IPC: H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L29/775 ,  H01L29/423

Abstract: Stacked transistor structures and methods of forming same. In an embodiment, a stacked transistor structure has a wide central pedestal region and at least one relatively narrower channel region above and/or below the wider central pedestal region. The upper and lower channel regions are configured with a non-planar architecture, and include one or more semiconductor fins, nanowires, and/or nanoribbons. The top and bottom channel regions may be configured the same or differently, with respect to shape and/or semiconductor materials. In some cases, an outermost sidewall of one or both the top and/or bottom channel region structures, is collinear with an outermost sidewall of the wider central pedestal region. In some such cases, the outermost sidewall of the top channel region structure is collinear with the outermost sidewall of the bottom channel region structure. Top and bottom transistor structures (NMOS/PMOS) may be formed using the top and bottom channel region structures.

公开(公告)号：US20200006329A1

公开(公告)日：2020-01-02

申请号：US16024058

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： AARON D. LILAK ,  GILBERT DEWEY ,  CHENG-YING HUANG ,  CHRISTOPHER JEZEWSKI ,  EHREN MANNEBACH ,  RISHABH MEHANDRU ,  PATRICK MORROW ,  ANAND S. MURTHY ,  ANH PHAN ,  WILLY RACHMADY

IPC: H01L27/088 ,  H01L23/522 ,  H01L23/48 ,  H01L21/768 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/092 ,  H01L23/00

Abstract: Stacked transistor structures having a conductive interconnect between source/drain regions of upper and lower transistors. In some embodiments, the interconnect is provided, at least in part, by highly doped epitaxial material deposited in the upper transistor's source/drain region. In such cases, the epitaxial material seeds off of an exposed portion of semiconductor material of or adjacent to the upper transistor's channel region and extends downward into a recess that exposes the lower transistor's source/drain contact structure. The epitaxial source/drain material directly contacts the lower transistor's source/drain contact structure, to provide the interconnect. In other embodiments, the epitaxial material still seeds off the exposed semiconductor material of or proximate to the channel region and extends downward into the recess, but need not contact the lower contact structure. Rather, a metal-containing contact structure passes through the epitaxial material of the upper source/drain region and contacts the lower transistor's source/drain contact structure.

公开(公告)号：US20200006559A1

公开(公告)日：2020-01-02

申请号：US16024046

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： RISHABH MEHANDRU ,  STEPHEN M. CEA ,  BISWAJEET GUHA ,  TAHIR GHANI ,  WILLIAM HSU

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/761 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423

Abstract: Isolation schemes for gate-all-around (GAA) transistor devices are provided herein. In some cases, the isolation schemes include changing the semiconductor nanowires/nanoribbons in a targeted channel region between active or functional transistor devices to electrically isolate those active devices. The targeted channel region is referred to herein as a dummy channel region, as it is not used as an actual channel region for an active or functional transistor device. The semiconductor nanowires/nanoribbons in the dummy channel region can be changed by converting them to an electrical insulator and/or by adding dopant that is opposite in type relative to surrounding source/drain material (to create a p-n junction). The isolation schemes described herein enable neighboring active devices to retain strain in the nanowires/nanoribbons of their channel regions, thereby improving device performance.

公开(公告)号：US20190341297A1

公开(公告)日：2019-11-07

申请号：US16473902

申请日：2017-03-30

Applicant: INTEL CORPORATION

Inventor： AARON D. LILAK ,  RISHABH MEHANDRU ,  PATRICK MORROW

IPC: H01L21/762 ,  H01L27/12 ,  H01L21/8234

Abstract: Techniques are disclosed for forming integrated circuit structures having a plurality of non-planar transistors. An insulation structure is provided between channel, source, and drain regions of neighboring fins. The insulation structure is formed during back side processing, wherein at least a first portion of the isolation material between adjacent fins is recessed to expose a sub-channel portion of the semiconductor fins. A spacer material is then deposited at least on the exposed opposing sidewalls of the exposed sub-channel portion of each fin. The isolation material is then further recessed to form an air gap between gate, source, and drain regions of neighboring fins. The air gap electrically isolates the source/drain regions of one fin from the source/drain regions of an adjacent fin, and likewise isolates the gate region of the one fin from the gate region of the adjacent fin. The air gap can be filled with a dielectric material.

公开(公告)号：US20190326290A1

公开(公告)日：2019-10-24

申请号：US16465039

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： STEPHEN M. CEA ,  RISHABH MEHANDRU ,  ANUPAMA BOWONDER ,  ANAND S. MURTHY ,  TAHIR GHANI

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/165 ,  H01L21/02 ,  H01L29/06

Abstract: Techniques are disclosed for forming dual-strain fins for co-integrated n-MOS and p-MOS devices. The techniques can be used to monolithically form tensile-strained fins to be used for n-MOS devices and compressive-strained fins to be used for p-MOS devices utilizing the same substrate, such that a single integrated circuit (IC) can include both of the devices. In some instances, the oppositely stressed fins may be achieved by employing a relaxed SiGe (rSiGe) layer from which the tensile and compressive-strained material can be formed. In some instances, the techniques include the formation of tensile-stressed Si and/or SiGe fins and compressive-stressed SiGe and/or Ge fins using a single relaxed SiGe layer to enable the co-integration of n-MOS and p-MOS devices, where each set of devices includes preferred materials and preferred stress/strain to enhance their respective performance. In some cases, improvements of at least 25% in drive current can be obtained.

公开(公告)号：US20200006488A1

公开(公告)日：2020-01-02

申请号：US16020361

申请日：2018-06-27

Applicant: INTEL CORPORATION

Inventor： RISHABH MEHANDRU ,  BISWAJEET GUHA ,  ANUPAMA BOWONDER ,  ANAND S. MURTHY ,  TAHIR GHANI ,  STEPHEN M. CEA

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78 ,  H01L21/74 ,  H01L29/66

Abstract: Integrated circuit structures including a buried etch-stop layer to help control transistor source/drain depth are provided herein. The buried etch-stop layer addresses the issue of the source/drain etch (or epi-undercut (EUC) etch) going below the bottom of the active height of the channel region, as such an issue can result in un-controlled sub-fin leakage that causes power consumption degradation and other undesired performance issues. The buried etch-stop layer is formed below the channel material, such as in the epitaxial stack that includes the channel material, and acts to slow the removal of material after the channel material has been removed when etching to form the source/drain trenches. In other words, the buried etch-stop layer includes different material from the channel material that can be etched, for at least one given etchant, at a relatively slower rate than the channel material to help control the source/drain trench depth.

公开(公告)号：US20180331183A1

公开(公告)日：2018-11-15

申请号：US15775786

申请日：2015-12-17

Applicant: Intel Corporation

Inventor： AARON D. LILAK ,  RISHABH MEHANDRU ,  HAROLD W. KENNEL ,  PAUL B. FISCHER ,  STEPHEN M. CEA

IPC: H01L29/10 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L23/00

CPC classification number: H01L29/1083 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L23/48 ,  H01L24/16 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/78 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/13067 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2224/13099

Abstract: Embodiments of the present disclosure describe techniques for backside isolation for devices of an integrated circuit (IC) and associated configurations. The IC may include a plurality of devices (e.g., transistors) formed on a semiconductor substrate. The semiconductor substrate may include substrate regions on which one or more devices are formed. Trenches may be disposed between the devices on the semiconductor substrate. Portions of the semiconductor substrate between the substrate regions may be removed to expose the corresponding trenches and form isolation regions. An insulating material may be formed in the isolation regions. Other embodiments may be described and/or claimed.

公开(公告)号：US20180151733A1

公开(公告)日：2018-05-31

申请号：US15575011

申请日：2015-06-19

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  PATRICK H. KEYS ,  HAROLD W. KENNEL ,  RISHABH MEHANDRU ,  ANAND S. MURTHY ,  KARTHIK JAMBUNATHAN

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/167 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/7848 ,  H01L27/0886 ,  H01L29/0603 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/167 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: Techniques are disclosed for forming p-MOS transistors having one or more carbon-based interface layers between epitaxially grown S/D regions and the channel region. In some cases, the carbon-based interface layer(s) may comprise a single layer having a carbon content of greater than 20% carbon and a thickness of 0.5-8 nm. In some cases, the carbon-based interface layer(s) may comprise a single layer having a carbon content of less than 5% and a thickness of 2-10 nm. In some such cases, the single layer may also comprise boron-doped silicon (Si:B) or boron-doped silicon germanium (SiGe:B). In some cases, one or more additional interface layers may be deposited on the carbon-based interface layer(s), where the additional interface layer(s) comprises Si:B and/or SiGe:B. The techniques can be used to improve short channel effects and improve the effective gate length of a resulting transistor.

公开(公告)号：US20180151732A1

公开(公告)日：2018-05-31

申请号：US15575008

申请日：2015-06-19

Applicant: INTEL CORPORATION

Inventor： RISHABH MEHANDRU ,  ANAND S. MURTHY ,  TAHIR GHANI ,  GLENN A. GLASS ,  KARTHIK JAMBUNATHAN ,  SEAN T. MA ,  CORY E. WEBER

IPC: H01L29/78 ,  H01L29/167 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66 ,  H01L21/306 ,  H01L21/02 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

Abstract: Techniques are disclosed for resistance reduction in p-MOS transistors having epitaxially grown boron-doped silicon germanium (SiGe:B) S/D regions. The techniques can include growing one or more interface layers between a silicon (Si) channel region of the transistor and the SiGe:B replacement S/D regions. The one or more interface layers may include: a single layer of boron-doped Si (Si:B); a single layer of SiGe:B, where the Ge content in the interface layer is less than that in the resulting SiGe:B S/D regions; a graded layer of SiGe:B, where the Ge content in the alloy starts at a low percentage (or 0%) and is increased to a higher percentage; or multiple stepped layers of SiGe:B, where the Ge content in the alloy starts at a low percentage (or 0%) and is increased to a higher percentage at each step. Inclusion of the interface layer(s) reduces resistance for on-state current flow.

公开(公告)号：US20200006331A1

公开(公告)日：2020-01-02

申请号：US16024080

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： AARON D. LILAK ,  GILBERT DEWEY ,  WILLY RACHMADY ,  RAMI HOURANI ,  STEPHANIE A. BOJARSKI ,  RISHABH MEHANDRU ,  ANH PHAN ,  EHREN MANNEBACH

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06

Abstract: A stacked transistor architecture has a fin structure that includes lower and upper portions separated by an isolation region built into the fin structure. Upper and lower gate structures on respective upper and lower fin structure portions may be different from one another (e.g., with respect to work function metal and/or gate dielectric thickness). One example methodology includes depositing lower gate structure materials on the lower and upper channel regions, recessing those materials to re-expose the upper channel region, and then re-depositing upper gate structure materials on the upper channel region. Another example methodology includes depositing a sacrificial protective layer on the upper channel region. The lower gate structure materials are then deposited on both the exposed lower channel region and sacrificial protective layer. The lower gate structure materials and sacrificial protective layer are then recessed to re-expose upper channel region so that upper gate structure materials can be deposited.