Invention Application
- Patent Title: CHANNEL LAYER FORMATION FOR III-V METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTORS (MOSFETS)
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Application No.: US16024701Application Date: 2018-06-29
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Publication No.: US20200006576A1Publication Date: 2020-01-02
- Inventor: Sean MA , Nicholas MINUTILLO , Cheng-Ying HUANG , Tahir GHANI , Jack KAVALIEROS , Anand MURTHY , Harold KENNEL , Gilbert DEWEY , Matthew METZ , Willy RACHMADY
- Applicant: Intel Corporation
- Main IPC: H01L29/786
- IPC: H01L29/786 ; H01L29/205 ; H01L29/423 ; H01L29/04 ; H01L29/66

Abstract:
Embodiments herein describe techniques, systems, and method for a semiconductor device. A semiconductor device may include isolation areas above a substrate to form a trench between the isolation areas. A first buffer layer is over the substrate, in contact with the substrate, and within the trench. A second buffer layer is within the trench over the first buffer layer, and in contact with the first buffer layer. A channel area is above the first buffer layer, above a portion of the second buffer layer that are below a source area or a drain area, and without being vertically above a portion of the second buffer layer. In addition, the source area or the drain area is above the second buffer layer, in contact with the second buffer layer, and adjacent to the channel area. Other embodiments may be described and/or claimed.
Public/Granted literature
- US11695081B2 Channel layer formation for III-V metal-oxide-semiconductor field effect transistors (MOSFETs) Public/Granted day:2023-07-04
Information query
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