• Patent Title: SiC SUBSTRATE EVALUATION METHOD AND METHOD FOR MANUFACTURING SiC EPITAXIAL WAFER
  • Application No.: US16598486
    Application Date: 2019-10-10
  • Publication No.: US20200116649A1
    Publication Date: 2020-04-16
  • Inventor: Yoshitaka NISHIHARAKoji KAMEI
  • Applicant: SHOWA DENKO K.K.
  • Applicant Address: JP Tokyo
  • Assignee: SHOWA DENKO K.K.
  • Current Assignee: SHOWA DENKO K.K.
  • Current Assignee Address: JP Tokyo
  • Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@9184e66
  • Main IPC: G01N21/88
  • IPC: G01N21/88
SiC SUBSTRATE EVALUATION METHOD AND METHOD FOR MANUFACTURING SiC EPITAXIAL WAFER
Abstract:
In a SiC substrate evaluation method, a bar-shaped stacking fault is observed by irradiating a surface of a SiC substrate before stacking an epitaxial layer with excitation light and extracting light having a wavelength range from equal to or greater than 405 nm and equal to or less than 445 nm among photoluminescence light beams emitted from the first surface.
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