Invention Application
- Patent Title: METHOD OF SINGULATING SEMICONDUCTOR WAFER HAVING A PLURALITY OF DIE AND A BACK LAYER DISPOSED ALONG A MAJOR SURFACE
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Application No.: US16715019Application Date: 2019-12-16
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Publication No.: US20200118878A1Publication Date: 2020-04-16
- Inventor: Gordon M. GRIVNA
- Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Applicant Address: US AZ Phoenix
- Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Current Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Current Assignee Address: US AZ Phoenix
- Main IPC: H01L21/78
- IPC: H01L21/78 ; H01L23/544 ; H01L21/67 ; B28D5/00 ; H01L21/3065 ; H01L21/477 ; H01L21/683

Abstract:
A method for forming an electronic device includes providing a wafer having a plurality of die formed as part of the wafer and separated from each other by spaces. A layer of material is disposed atop a major surface of the wafer and the layer of material is placed adjacent to first carrier substrate comprising a first adhesive layer. The wafer is singulated through the spaces to form singulation lines. A second carrier substrate comprising a second adhesive layer is placed onto an opposite major surface of the wafer. The method includes moving a mechanical device adjacent to and in a direction generally parallel to one of the first carrier substrate or the second carrier substrate to separate the layer of material in the singulation lines. In one example, the second adhesive layer has an adhesive strength that is less than that of the first adhesive layer.
Public/Granted literature
- US10770350B2 Method of separating a back layer on a singulated semiconductor wafer attached to carrier substrate Public/Granted day:2020-09-08
Information query
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