Invention Application
- Patent Title: 3D IC BUMP HEIGHT METROLOGY APC
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Application No.: US16735973Application Date: 2020-01-07
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Publication No.: US20200152495A1Publication Date: 2020-05-14
- Inventor: Nai-Han Cheng , Chi-Ming Yang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Main IPC: H01L21/67
- IPC: H01L21/67 ; H01L21/66 ; G01B11/24 ; G01B11/14 ; G01B11/16

Abstract:
The present disclosure, in some embodiments, relates to a substrate metrology system. The substrate metrology system includes a warpage measurement module configured to determine one or more substrate warpage parameters of a substrate. The substrate includes a plurality of conductive interconnect layers within a dielectric structure over a semiconductor substrate. A metrology module is located physically downstream of the warpage measurement module and has an optical element configured to measure one or more dimensions of the substrate. The metrology module is configured to place the optical element at a plurality of different initial positions, which are directly over a plurality of different locations on the substrate, based upon the one or more substrate warpage parameters. A substrate transport system is configured to transfer the substrate from a first position within the warpage measurement module to a non-overlapping second position within the metrology module.
Public/Granted literature
- US11075097B2 3D IC bump height metrology APC Public/Granted day:2021-07-27
Information query
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