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    3D IC BUMP HEIGHT METROLOGY APC
    2.
    发明申请
    3D IC BUMP HEIGHT METROLOGY APC 审中-公开

    公开(公告)号：US20200152495A1

    公开(公告)日：2020-05-14

    申请号：US16735973

    申请日：2020-01-07

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Nai-Han Cheng ,  Chi-Ming Yang

    IPC: H01L21/67 ,  H01L21/66 ,  G01B11/24 ,  G01B11/14 ,  G01B11/16

    Abstract: The present disclosure, in some embodiments, relates to a substrate metrology system. The substrate metrology system includes a warpage measurement module configured to determine one or more substrate warpage parameters of a substrate. The substrate includes a plurality of conductive interconnect layers within a dielectric structure over a semiconductor substrate. A metrology module is located physically downstream of the warpage measurement module and has an optical element configured to measure one or more dimensions of the substrate. The metrology module is configured to place the optical element at a plurality of different initial positions, which are directly over a plurality of different locations on the substrate, based upon the one or more substrate warpage parameters. A substrate transport system is configured to transfer the substrate from a first position within the warpage measurement module to a non-overlapping second position within the metrology module.

    3D IC bump height metrology APC
    3.
    发明授权
    3D IC bump height metrology APC 有权

    公开(公告)号：US10181415B2

    公开(公告)日：2019-01-15

    申请号：US15831806

    申请日：2017-12-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Nai-Han Cheng ,  Chi-Ming Yang

    IPC: G01B11/02 ,  G01B11/24 ,  H01L21/67 ,  G01B11/16 ,  G01B11/14 ,  H01L21/66 ,  H01L23/00 ,  H01L21/768 ,  H01L25/00 ,  H01L25/065

    Abstract: In some embodiments, the present disclosure relates to a method of bump metrology The method is performed by forming a through-substrate-via within a substrate, forming a plurality of metal interconnect layers within a dielectric structure over the substrate, and forming a bump on the plurality of metal interconnect layers. One or more substrate warpage parameters of the substrate are measured and an initial position of a lens within a substrate metrology module is calculated based upon the one or more substrate warpage parameters. The lens is then moved to the initial position, and a height and a width of the bump are measured using the substrate metrology module after moving the lens to the initial position.

    Bottom-up PEALD proces
    4.
    发明授权
    Bottom-up PEALD proces 有权

    公开(公告)号：US10121653B2

    公开(公告)日：2018-11-06

    申请号：US14861441

    申请日：2015-09-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Lin-Jung Wu ,  Su-Horng Lin ,  Chi-Ming Yang

    IPC: H01L21/00 ,  H01L21/02 ,  H01J37/32 ,  C23C16/04 ,  C23C16/455 ,  H01L21/285 ,  H01L21/687

    Abstract: The present disclosure relates to a method and apparatus for performing a plasma enhanced ALD (PEALD) process that provides for improved step coverage. The process introduces a precursor gas into a processing chamber comprising a semiconductor workpiece. The first gas is ionized to form a plurality of ionized precursor molecules. A bias voltage is subsequently applied to the workpiece. The bias voltage attracts the ionized precursor molecules to the workpiece, so as to provide anisotropic coverage of the workpiece with the precursor gas. A reactant gas is introduced into the processing chamber. A plasma is subsequently ignited from the reactant gas, causing the reactant gas to react with the ionized precursor molecules that have been deposited onto the substrate to form a deposited layer on the workpiece.

    Bottom-up PEALD process
    6.
    发明授权
    Bottom-up PEALD process 有权
    自下而上的PEALD过程

    公开(公告)号：US09184045B2

    公开(公告)日：2015-11-10

    申请号：US13762547

    申请日：2013-02-08

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Lin-Jung Wu ,  Su-Horng Lin ,  Chi-Ming Yang

    IPC: H01L21/00 ,  H01L21/02 ,  H01J37/32

    CPC classification number: H01L21/0228 ,  C23C16/045 ,  C23C16/45542 ,  H01J37/321 ,  H01J37/3211 ,  H01J37/32357 ,  H01J37/32706 ,  H01J37/32926 ,  H01L21/02274 ,  H01L21/28556 ,  H01L21/687

    Abstract: The present disclosure relates to a method and apparatus for performing a plasma enhanced ALD (PEALD) process that provides for improved step coverage. The process introduces a precursor gas into a processing chamber comprising a semiconductor workpiece. The first gas is ionized to from a plurality of ionized precursor molecules. A bias voltage is subsequently applied to the workpiece. The bias voltage attracts the ionized precursor molecules to the workpiece, so as to provide anisotropic coverage of the workpiece with the precursor gas. A reactant gas is introduced into the processing chamber. A plasma is subsequently ignited from the reactant gas, causing the reactant gas to react with the ionized precursor molecules that have been deposited onto the substrate to form a deposited layer on the workpiece.

    Abstract translation: 本公开涉及一种用于执行等离子体增强ALD（PEALD）过程的方法和装置，其提供改进的步骤覆盖。 该方法将前体气体引入到包括半导体工件的处理室中。 将第一气体从多个离子化的前体分子离子化。 随后将偏置电压施加到工件。 偏置电压将离子化的前体分子吸引到工件，以便为前体气体提供工件的各向异性覆盖。 将反应气体引入处理室。 等离子体随后从反应气体中点燃，使反应气体与沉积在基底上的离子化前体分子反应，在工件上形成沉积层。

    METHOD OF SELECTIVELY REMOVING SILICON NITRIDE AND ETCHING APPARATUS THEREOF
    7.
    发明申请
    METHOD OF SELECTIVELY REMOVING SILICON NITRIDE AND ETCHING APPARATUS THEREOF 有权
    选择性除去硅氮化物及其蚀刻装置的方法

    公开(公告)号：US20150111311A1

    公开(公告)日：2015-04-23

    申请号：US14056673

    申请日：2013-10-17

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Ying-Hsueh CHANGCHIEN ,  Yu-Ming Lee ,  Chi-Ming Yang

    IPC: H01L21/311 ,  H01L21/67 ,  H01L21/66

    CPC classification number: H01L21/31111

    Abstract: A method of selectively removing silicon nitride is provided. The method includes: providing a wafer having silicon nitride on a surface of the wafer; supplying a mixture of phosphoric acid and a silicon-containing material into a process tank, in which the mixture has a predetermined silicon concentration; and submerging the wafer into the mixture within the process tank to remove the silicon nitride. An etching apparatus of selectively removing silicon nitride is also provided.

    Abstract translation: 提供了选择性去除氮化硅的方法。 该方法包括：在晶片的表面上提供具有氮化硅的晶片; 将磷酸和含硅材料的混合物供应到处理罐中，其中混合物具有预定的硅浓度; 并将晶片浸没在处理槽内的混合物中以除去氮化硅。 还提供了选择性地去除氮化硅的蚀刻装置。

    3D IC BUMP HEIGHT METROLOGY APC
    10.
    发明申请
    3D IC BUMP HEIGHT METROLOGY APC 审中-公开

    公开(公告)号：US20190139800A1

    公开(公告)日：2019-05-09

    申请号：US16234675

    申请日：2018-12-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Nai-Han Cheng ,  Chi-Ming Yang

    IPC: H01L21/67 ,  G01B11/14 ,  G01B11/24 ,  H01L21/66 ,  G01B11/16 ,  H01L23/00 ,  H01L21/768 ,  H01L25/00 ,  H01L25/065

    Abstract: The present disclosure, in some embodiments, relates to a substrate metrology system. The substrate metrology system includes a substrate warpage measurement module configured to determine one or more substrate warpage parameters of a substrate by taking a plurality of separate measurements at a plurality of different positions over a substrate. The substrate has a plurality of conductive interconnect layers within a dielectric structure over a semiconductor substrate and a conductive bump disposed over the dielectric structure and configured to be coupled to an additional substrate of a multi-dimensional chip. A substrate metrology module has an optical component and is configured to measure one or more dimensions of the conductive bump. A position control element is configured to move the optical component. A feed-forward path is coupled between an output of the substrate warpage measurement module and an input of the position control element.

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