- 专利标题: PHASE ERROR REDUCTION IN A RECEIVER
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申请号: US16793486申请日: 2020-02-18
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公开(公告)号: US20200186403A1公开(公告)日: 2020-06-11
- 发明人: Yogesh DARWHEKAR , Pranav KUMAR , Arpan THAKKAR , Naveen MAHADEV , Srikanth MANIAN
- 申请人: TEXAS INSTRUMENTS INCORPORATED
- 主分类号: H04L27/00
- IPC分类号: H04L27/00 ; H04L27/38 ; H04L27/152 ; H04L27/148
摘要:
A receiver circuit includes a quadrature signal generator to generate an in-phase (I) signal and a quadrature (Q) signal from a local oscillator signal and an IQ phase sense and control circuit to generate a phase adjustment code responsive to a phase error between quadrature signals generated by a plurality of mixers. The receiver circuit also includes a phase corrector to adjust a phase difference between the I and Q signals from the quadrature signal generator to generate corrected I and Q signals to be provided to the plurality of mixers.
公开/授权文献
- US10924309B2 Phase error reduction in a receiver 公开/授权日:2021-02-16
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