公开(公告)号：US20200092148A1

公开(公告)日：2020-03-19

申请号：US16130087

申请日：2018-09-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yogesh DARWHEKAR ,  Pranav KUMAR ,  Arpan THAKKAR ,  Naveen MAHADEV ,  Srikanth MANIAN

IPC: H04L27/00 ,  H04L27/38 ,  H04L27/148 ,  H04L27/152

Abstract: A receiver circuit includes a quadrature signal generator to generate an in-phase (I) signal and a quadrature (Q) signal from a local oscillator signal and an IQ phase sense and control circuit to generate a phase adjustment code responsive to a phase error between quadrature signals generated by a plurality of mixers. The receiver circuit also includes a phase corrector to adjust a phase difference between the I and Q signals from the quadrature signal generator to generate corrected I and Q signals to be provided to the plurality of mixers.

公开(公告)号：US20190252373A1

公开(公告)日：2019-08-15

申请号：US15990880

申请日：2018-05-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Pranav KUMAR ,  Yogesh DARWHEKAR

IPC: H01L27/06 ,  H01L29/73 ,  H03K19/018

CPC classification number: H01L27/0647 ,  H01L29/7302 ,  H03K19/01825 ,  H03K19/01837

Abstract: A circuit includes a first bipolar junction transistor (BJT) including a first base, a first collector, and a first emitter, the first collector connected to a first supply voltage node and a second BJT including a second base, a second collector, and a second emitter, the second collector connected to the first emitter at an output node. The circuit also includes a capacitor including a first capacitor terminal and a second capacitor terminal, the first capacitor terminal connected to the second emitter of the second BJT and the second capacitor terminal connected to a second supply voltage node. A current source device is also included that is connected in parallel with the capacitor.

公开(公告)号：US20210391866A1

公开(公告)日：2021-12-16

申请号：US17128791

申请日：2020-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Srinivas THEERTHAM ,  Jagdish CHAND ,  Yogesh DARWHEKAR ,  Subhashish MUKHERJEE ,  Jayawardan JANARDHANAN ,  Uday Kiran MEDA ,  Arpan Sureshbhai THAKKAR ,  Apoorva BHATIA ,  Pranav KUMAR

IPC: H03L7/23 ,  H03L7/099 ,  H03L7/085 ,  H03M1/66

Abstract: A frequency synthesizer includes a phase-locked loop (PLL). The PLL includes a first voltage-controlled oscillator (VCO) and a second VCO, each comprising an oscillator, a capacitor bank, and a bias circuit. The capacitor bank is configured to selectably adjust an output frequency of the oscillator. The bias circuit is configured to provide a bias current to the oscillator, and includes a current digital-to-analog converter (IDAC), and an amplifier coupled to the IDAC and configured to drive the oscillator.

公开(公告)号：US20200186403A1

公开(公告)日：2020-06-11

申请号：US16793486

申请日：2020-02-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yogesh DARWHEKAR ,  Pranav KUMAR ,  Arpan THAKKAR ,  Naveen MAHADEV ,  Srikanth MANIAN

IPC: H04L27/00 ,  H04L27/38 ,  H04L27/152 ,  H04L27/148

Abstract: A receiver circuit includes a quadrature signal generator to generate an in-phase (I) signal and a quadrature (Q) signal from a local oscillator signal and an IQ phase sense and control circuit to generate a phase adjustment code responsive to a phase error between quadrature signals generated by a plurality of mixers. The receiver circuit also includes a phase corrector to adjust a phase difference between the I and Q signals from the quadrature signal generator to generate corrected I and Q signals to be provided to the plurality of mixers.

公开(公告)号：US20220382320A1

公开(公告)日：2022-12-01

申请号：US17683185

申请日：2022-02-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Apoorva BHATIA ,  Pranav KUMAR ,  Abhrarup BARMAN ROY ,  Peeyoosh MIRAJKAR ,  Raghavendra REDDY

IPC: G06F1/12 ,  H03K19/20 ,  H03K3/037 ,  G06F1/08

Abstract: In an example, a system is adapted to be coupled to a load device having a load clock. The system includes a clock generation device with a pin. The system also includes a capture circuit coupled to the pin and operable to sample a value at the pin. The system includes a D flip-flop having a data input coupled to the capture circuit, a clock input coupled to a clock, and having an output, where the D flip-flop is operable to provide, at the output, a system reference event (SYSREF) signal to align the load clock to the clock, based at least in part on the value at the pin.