中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

7 records (took 0.014 seconds)

    FREQUENCY SYNTHESIZER FOR ACHIEVING FAST RE-LOCK BETWEEN ALTERNATE FREQUENCIES IN LOW BANDWIDTH PLLS
    2.
    发明申请
    FREQUENCY SYNTHESIZER FOR ACHIEVING FAST RE-LOCK BETWEEN ALTERNATE FREQUENCIES IN LOW BANDWIDTH PLLS 有权
    用于实现低频带中替代频率之间快速重锁的频率合成器

    公开(公告)号：US20150381190A1

    公开(公告)日：2015-12-31

    申请号：US14753940

    申请日：2015-06-29

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Jagdish Chand GOYAL ,  Krishnaswamy THIAGARAJAN ,  Jayawardan JANARDHANAN ,  Srikanth MANIAN

    IPC: H03L7/093 ,  H03L7/089 ,  H03L7/081 ,  H04B1/40

    CPC classification number: H04B1/40 ,  H03L7/1075 ,  H03L7/1976

    Abstract: A frequency synthesizer that includes a reference frequency scaler and a phase locked loop (PLL) coupled to the reference frequency scaler. The reference frequency scaler is configured to generate a first reference frequency and a second reference frequency. The PLL is configured to generate a first output frequency based on the first reference frequency during a first timeslot and a second output frequency based on the second reference frequency during a second timeslot. The PLL comprises a loop filter that includes a first switch connected in series to a first capacitor and configured to close during the first timeslot and a second switch connected in series to a second capacitor and configured to open during the first timeslot.

    Abstract translation: 一种频率合成器，其包括参考频率缩放器和耦合到参考频率缩放器的锁相环（PLL）。 参考频率缩放器被配置为产生第一参考频率和第二参考频率。 PLL被配置为在第一时隙期间基于第一参考频率产生第一输出频率，并且在第二时隙期间基于第二参考频率产生第二输出频率。 PLL包括环路滤波器，其包括串联连接到第一电容器并被配置为在第一时隙期间闭合的第一开关和与第二电容器串联连接并被配置为在第一时隙期间断开的第二开关。

    FRACTIONAL-N SYNTHESIZER WITH PRE-MULTIPLICATION
    4.
    发明申请
    FRACTIONAL-N SYNTHESIZER WITH PRE-MULTIPLICATION 有权
    具有预处理功能的合成N合成器

    公开(公告)号：US20150326236A1

    公开(公告)日：2015-11-12

    申请号：US14709759

    申请日：2015-05-12

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Krishnaswamy THIAGARAJAN ,  Jagdish Chand GOYAL ,  Srikanth MANIAN ,  Debapriya SAHU

    IPC: H03L7/197 ,  H04L7/033 ,  H04B1/40

    CPC classification number: H03L7/1976 ,  H03L7/0814 ,  H03L7/1974 ,  H03L2207/10 ,  H04B1/40 ,  H04L7/033 ,  H04L7/0331

    Abstract: A fractional-N frequency synthesizer that suppresses integer boundary spurs. A frequency synthesizer includes a fractional-N phase locked loop (PLL) and a reference frequency scaler. The reference frequency scaler is coupled to a reference clock input of the PLL, the reference frequency scaler includes a programmable frequency divider, and a programmable frequency multiplier connected in series with the programmable frequency divider. Each of the divider and multiplier is configured to scale a reference frequency provided to the PLL by a programmable integer value.

    Abstract translation: 一个抑制整数边界杂散的分数N频率合成器。 频率合成器包括分数N锁相环（PLL）和参考频率缩放器。 参考频率缩放器耦合到PLL的参考时钟输入，参考频率缩放器包括可编程分频器和与可编程分频器串联连接的可编程倍频器。 分频器和乘法器中的每一个被配置为通过可编程整数值来缩放提供给PLL的参考频率。

    SERIAL BUS REDRIVER WITH TRAILING EDGE BOOST CIRCUIT
    5.
    发明公开
    SERIAL BUS REDRIVER WITH TRAILING EDGE BOOST CIRCUIT 审中-公开

    公开(公告)号：US20230318587A1

    公开(公告)日：2023-10-05

    申请号：US18329805

    申请日：2023-06-06

    Applicant: Texas Instruments Incorporated

    Inventor： Srijan RASTOGI ,  Srikanth MANIAN

    IPC: H03K3/037 ,  H03K19/20 ,  H03K5/01

    CPC classification number: H03K5/01 ,  H03K3/037 ,  H03K19/20 ,  H03K2005/00019

    Abstract: A serial bus re-driver circuit includes an edge detector circuit and a booster circuit. The edge detector circuit is configured to detect a transition of serial bus signal. The booster circuit is coupled to the edge detector circuit, and is configured to switch current to the serial bus signal. The booster circuit includes a leading edge boost pulse generation circuit and a trailing edge boost pulse generation circuit. The leading edge boost pulse generation circuit is configured to switch a first current pulse to the serial bus signal at the transition of the serial bus signal. The trailing edge boost pulse generation circuit is configured to switch a second current pulse to the serial bus signal. The second current pulse is shorter than the first current pulse.

    VOLTAGE-CONTROLLED OSCILLATOR (VCO) WITH LC CIRCUIT AND SERIES RESISTORS
    6.
    发明申请
    VOLTAGE-CONTROLLED OSCILLATOR (VCO) WITH LC CIRCUIT AND SERIES RESISTORS 有权

    公开(公告)号：US20220038056A1

    公开(公告)日：2022-02-03

    申请号：US17493922

    申请日：2021-10-05

    Applicant: Texas Instruments Incorporated

    Inventor： Srinivas THEERTHAM ,  Srikanth MANIAN ,  Uday Kiran MEDA

    IPC: H03B5/12 ,  H03L7/099

    Abstract: A system includes a data path and a phase-locked loop (PLL) coupled to the data path. The system also includes a voltage-controlled oscillator (VCO) coupled to the PLL. The VCO includes an LC circuit with first and second differential output terminals. The VCO also includes a first resistor coupled between the first differential output terminal and drain terminals of a first pair of complementary metal-oxide semiconductor (CMOS) transistors. The VCO also includes a second resistor coupled between the second differential output terminal and drain terminals of a second pair of CMOS transistors.

Patent Agency Ranking