- 专利标题： METHODS OF FABRICATING SEMICONDUCTOR DEVICES WITH MIXED THRESHOLD VOLTAGES BOUNDARY ISOLATION OF MULTIPLE GATES AND STRUCTURES FORMED THEREBY
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申请号： US16353012申请日： 2019-03-14
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公开(公告)号： US20200294863A1公开(公告)日： 2020-09-17
- 发明人: Kuo-Cheng CHIANG , Chung-Wei HSU , Lung-Kun CHU , Jia-Ni YU , Chih-Hao WANG , Mao-Lin HUANG
- 申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- 申请人地址： TW Hsinchu
- 专利权人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- 当前专利权人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- 当前专利权人地址： TW Hsinchu
- 主分类号： H01L21/8238
- IPC分类号： H01L21/8238 ; H01L29/78 ; H01L29/06 ; H01L29/66 ; H01L29/49 ; H01L27/092 ; H01L21/308 ; H01L21/033 ; H01L21/28
摘要：
A method of fabricating semiconductor devices includes forming a plurality of first and second nanosheets in p-type and n-type device regions, respectively. A p-type work function (PWF) layer is deposited to surround each of the first and second nanosheets. A first mask is formed on the PWF layer and not over the boundary between the p-type and n-type device regions, and then the PWF layer is etched in a first etching process to keep portions of the PWF layer between the second nanosheets. A second mask is formed on the PWF layer, and then the portions of the PWF layer between the second nanosheets are removed in a second etching process. An n-type work function layer is deposited in the n-type and the p-type device regions to surround each of the second nanosheets and on the PWF layer.
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