公开(公告)号：US20240014265A1

公开(公告)日：2024-01-11

申请号：US18188306

申请日：2023-03-22

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Lung-Kun CHU ,  Jia-Ni YU ,  Chun-Fu LU ,  Chung-Wei HSU ,  Mao-Lin HUANG ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC分类号： H01L29/06 ,  H01L29/786 ,  H01L29/775 ,  H01L29/66 ,  H01L29/423 ,  H01L27/092 ,  H01L21/8238

CPC分类号： H01L29/0673 ,  H01L29/78696 ,  H01L29/775 ,  H01L29/66439 ,  H01L29/42392 ,  H01L27/092 ,  H01L21/823807 ,  H01L21/823878

摘要： The present disclosure describes a semiconductor device having an isolation structure. The semiconductor structure includes a set of nanostructures on a substrate, a gate dielectric layer wrapped around the set of nanostructures, a work function metal layer on the gate dielectric layer and around the set of nanostructures, and the isolation structure adjacent to the set of nanostructures and in contact with the work function metal layer. A portion of the work function metal layer is on a top surface of the isolation structure.

公开(公告)号：US20200294863A1

公开(公告)日：2020-09-17

申请号：US16353012

申请日：2019-03-14

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Kuo-Cheng CHIANG ,  Chung-Wei HSU ,  Lung-Kun CHU ,  Jia-Ni YU ,  Chih-Hao WANG ,  Mao-Lin HUANG

IPC分类号： H01L21/8238 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/49 ,  H01L27/092 ,  H01L21/308 ,  H01L21/033 ,  H01L21/28

摘要： A method of fabricating semiconductor devices includes forming a plurality of first and second nanosheets in p-type and n-type device regions, respectively. A p-type work function (PWF) layer is deposited to surround each of the first and second nanosheets. A first mask is formed on the PWF layer and not over the boundary between the p-type and n-type device regions, and then the PWF layer is etched in a first etching process to keep portions of the PWF layer between the second nanosheets. A second mask is formed on the PWF layer, and then the portions of the PWF layer between the second nanosheets are removed in a second etching process. An n-type work function layer is deposited in the n-type and the p-type device regions to surround each of the second nanosheets and on the PWF layer.

公开(公告)号：US20240145470A1

公开(公告)日：2024-05-02

申请号：US18406025

申请日：2024-01-05

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Lung-Kun CHU ,  Mao-Lin HUANG ,  Chung-Wei HSU ,  Jia-Ni YU ,  Kuo-Cheng CHIANG ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC分类号： H01L27/0883 ,  H01L21/823412 ,  H01L21/823462 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696

摘要： A method for processing an integrated circuit includes forming first and second gate all around transistors. The method forms a dipole oxide in the first gate all around transistor without forming the dipole oxide in the second gate all around transistor. This is accomplished by entirely removing an interfacial dielectric layer and a dipole-inducing layer from semiconductor nanosheets of the second gate all around transistor before redepositing the interfacial dielectric layer on the semiconductor nanosheets of the second gate all around transistor.

公开(公告)号：US20190103283A1

公开(公告)日：2019-04-04

申请号：US16053981

申请日：2018-08-03

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chen-Hao WU ,  Shen-Nan LEE ,  Chung-Wei HSU ,  Tsung-Ling TSAI ,  Teng-Chun TSAI

IPC分类号： H01L21/321 ,  H01L21/768 ,  H01L29/66 ,  H01L29/417

摘要： A method for manufacturing a semiconductor device includes forming a gate electrode over a substrate; forming a hard mask over the gate electrode, in which the hard mask comprises a metal oxide; forming an interlayer dielectric (ILD) layer over the hard mask; forming a contact hole in the ILD layer, wherein the contact hole exposes a source/drain; filling the contact hole with a conductive material; and applying a chemical mechanical polish process to the ILD layer and the conductive material, wherein the chemical mechanical polish process stops at the hard mask, the chemical mechanical polish process uses a slurry containing a boric acid or its derivative, the chemical mechanical polish process has a first removal rate of the ILD layer and a second removal rate of the hard mask, and a first ratio of the first removal rate to the second removal rate is greater than about 5.

公开(公告)号：US20240312993A1

公开(公告)日：2024-09-19

申请号：US18354515

申请日：2023-07-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chung-Wei HSU ,  Lung-Kun CHU ,  Jia-Ni YU ,  Chun-Fu LU ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

摘要： An integrated circuit includes an NMOS gate all around (GAA) transistor and a PMOS GAA transistor. A single gate metal is utilized for both transistors. An effective work function is imparted to the NMOS transistor by including a first layer of the gate metal around the channels, a semiconductor layer around the first layer of the gate metal, and a gate fill layer of the gate metal on the semiconductor layer. The PMOS transistor, the gate fill layer of the gate metal is on the gate dielectric without an intervening semiconductor layer.

公开(公告)号：US20230010502A1

公开(公告)日：2023-01-12

申请号：US17370843

申请日：2021-07-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Lung-Kun CHU ,  Mao-Lin HUANG ,  Chung-Wei HSU ,  Jia-Ni YU ,  Kuo-Cheng CHIANG ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC分类号： H01L27/088 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L21/8234

摘要： A method for processing an integrated circuit includes forming first and second gate all around transistors. The method forms a dipole oxide in the first gate all around transistor without forming the dipole oxide in the second gate all around transistor. This is accomplished by entirely removing an interfacial dielectric layer and a dipole-inducing layer from semiconductor nanosheets of the second gate all around transistor before redepositing the interfacial dielectric layer on the semiconductor nanosheets of the second gate all around transistor.

公开(公告)号：US20220115498A1

公开(公告)日：2022-04-14

申请号：US17070717

申请日：2020-10-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Lung-Kun CHU ,  Mao-Lin HUANG ,  Chung-Wei HSU ,  Jia-Ni YU ,  Kuo-Cheng CHIANG ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC分类号： H01L29/06 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

摘要： A device includes a substrate, and a first semiconductor channel over the substrate. The first semiconductor channel includes a first nanosheet of a first semiconductor material, a second nanosheet of a second semiconductor material in physical contact with a topside surface of the first nanosheet, and a third nanosheet of the second semiconductor material in physical contact with an underside surface of the first nanosheet. The first gate structure is over and laterally surrounding the first semiconductor channel, and in physical contact with the second nanosheet and the third nanosheet.

公开(公告)号：US20230029370A1

公开(公告)日：2023-01-26

申请号：US17381006

申请日：2021-07-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Mao-Lin HUANG ,  Lung-Kun CHU ,  Chung-Wei HSU ,  Jia-Ni YU ,  Kuo-Cheng CHIANG ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC分类号： H01L21/28 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

摘要： A method for processing an integrated circuit includes forming N-type and P-type gate all around transistors and core gate all around transistors. The method deposits a metal gate layer for the P-type transistors. The method forms a passivation layer in-situ with the metal gate layer of the P-type transistor.

公开(公告)号：US20230009349A1

公开(公告)日：2023-01-12

申请号：US17370822

申请日：2021-07-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jia-Ni YU ,  Kuo-Cheng CHIANG ,  Mao-Lin HUANG ,  Lung-Kun CHU ,  Chung-Wei HSU ,  Chih-Hao WANG ,  Kuan-Lun CHENG

IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/51 ,  H01L21/8234

摘要： A method for processing an integrated circuit includes forming I/O gate all around transistors and core gate all around transistors. The method performs a regrowth process on an interfacial gate dielectric layer of the I/O gate all around transistors by diffusing metal atoms into the interfacial dielectric layer I/O gate all around transistor. The regrowth process does not diffuse metal atoms into the interfacial gate dielectric layer of the gate all around core transistor.

公开(公告)号：US20220320090A1

公开(公告)日：2022-10-06

申请号：US17476140

申请日：2021-09-15

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chung-Wei HSU ,  Kuo-Cheng CHIANG ,  Mao-Lin HUANG ,  Lung-Kun CHU ,  Jia-Ni YU ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC分类号： H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/66

摘要： A semiconductor device is provided. The semiconductor device includes first channel nanostructures in a first device region and second channel nanostructures in a second device region. The first channel nanostructures are disposed between first and second dielectric fins. The second channel nanostructures are disposed between first and third dielectric fins. A gate dielectric layer is formed to surround each of the first and the second channel nanostructures and over the first, the second and the third dielectric fins. A first work function layer is formed to surround each of the first channel nanostructures. A second work function layer is formed to surround each of the second channel nanostructures. A first gap is present between every adjacent first channel nanostructures and a second gap present is between every adjacent second channel nanostructures.