Invention Application
- Patent Title: METHODS TO PATTERN TFC AND INCORPORATION IN THE ODI ARCHITECTURE AND IN ANY BUILD UP LAYER OF ORGANIC SUBSTRATE
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Application No.: US16353164Application Date: 2019-03-14
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Publication No.: US20200294938A1Publication Date: 2020-09-17
- Inventor: Rahul JAIN , Kyu-Oh LEE , Islam A. SALAMA , Amruthavalli P. ALUR , Wei-Lun K. JEN , Yongki MIN , Sheng C. LI
- Applicant: Intel Corporation
- Main IPC: H01L23/64
- IPC: H01L23/64 ; H01L23/498 ; H01L49/02 ; H01L23/538

Abstract:
Embodiments include semiconductor packages. A semiconductor package includes a plurality of build-up layers and a plurality of conductive layers in the build-up layers. The conductive layers include a first conductive layer and a second conductive layer. The first conductive layer is over the second conductive layer and build-up layers, where a first via couples the first and second conductive layers. The semiconductor package also includes a thin film capacitor (TFC) in the build-up layers, where a second via couples the TFC to the first conductive layer, and the second via has a thickness less than a thickness of the first via. The first conductive layer may be first level interconnects. The build-up layers may be dielectrics. The TFC may include a first electrode, a second electrode, and a dielectric. The first electrode may be over the second electrode, and the dielectric may be between the first and second electrodes.
Public/Granted literature
Information query
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