公开(公告)号：US20200294938A1

公开(公告)日：2020-09-17

申请号：US16353164

申请日：2019-03-14

Applicant: Intel Corporation

Inventor： Rahul JAIN ,  Kyu-Oh LEE ,  Islam A. SALAMA ,  Amruthavalli P. ALUR ,  Wei-Lun K. JEN ,  Yongki MIN ,  Sheng C. LI

IPC: H01L23/64 ,  H01L23/498 ,  H01L49/02 ,  H01L23/538

Abstract: Embodiments include semiconductor packages. A semiconductor package includes a plurality of build-up layers and a plurality of conductive layers in the build-up layers. The conductive layers include a first conductive layer and a second conductive layer. The first conductive layer is over the second conductive layer and build-up layers, where a first via couples the first and second conductive layers. The semiconductor package also includes a thin film capacitor (TFC) in the build-up layers, where a second via couples the TFC to the first conductive layer, and the second via has a thickness less than a thickness of the first via. The first conductive layer may be first level interconnects. The build-up layers may be dielectrics. The TFC may include a first electrode, a second electrode, and a dielectric. The first electrode may be over the second electrode, and the dielectric may be between the first and second electrodes.

公开(公告)号：US20230245940A1

公开(公告)日：2023-08-03

申请号：US18133868

申请日：2023-04-12

Applicant: Intel Corporation

Inventor： Rahul JAIN ,  Kyu Oh LEE ,  Siddharth K. ALUR ,  Wei-Lun K. JEN ,  Vipul V. MEHTA ,  Ashish DHALL ,  Sri Chaitra J. CHAVALI ,  Rahul N. MANEPALLI ,  Amruthavalli P. ALUR ,  Sai VADLAMANI

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L23/532 ,  H01L23/498

CPC classification number: H01L23/3185 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0655 ,  H01L23/53295 ,  H01L23/3128 ,  H01L24/06 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/16227 ,  H01L2924/18161 ,  H01L2224/83051 ,  H01L2224/81

Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.

公开(公告)号：US20220199503A1

公开(公告)日：2022-06-23

申请号：US17129846

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Manish DUBEY ,  Guruprasad ARAKERE ,  Deepak KULKARNI ,  Sairam AGRAHARAM ,  Wei-Lun K. JEN ,  Numair AHMED ,  Kousik GANESAN ,  Amol D. JADHAV ,  Kyu-Oh LEE

IPC: H01L23/498 ,  H01L21/48

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a package substrate with a die side and a land side. In an embodiment, a pad is on the land side. In an embodiment, a dielectric layer covers sidewalls of the pad, and a surface finish is over an exposed surface of the pad.

公开(公告)号：US20240186202A1

公开(公告)日：2024-06-06

申请号：US18415268

申请日：2024-01-17

Applicant: Intel Corporation

Inventor： Rahul JAIN ,  Kyu Oh LEE ,  Siddharth K. ALUR ,  Wei-Lun K. JEN ,  Vipul V. MEHTA ,  Ashish DHALL ,  Sri Chaitra J. CHAVALI ,  Rahul N. MANEPALLI ,  Amruthavalli P. ALUR ,  Sai VADLAMANI

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L23/532 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/3185 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/53295 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16227 ,  H01L2224/81 ,  H01L2224/83051 ,  H01L2924/18161

Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.

公开(公告)号：US20210035818A1

公开(公告)日：2021-02-04

申请号：US16525985

申请日：2019-07-30

Applicant: Intel Corporation

Inventor： Tarek A. IBRAHIM ,  Rahul N. MANEPALLI ,  Wei-Lun K. JEN ,  Steve S. CHO ,  Jason M. GAMBA ,  Javier SOTO GONZALEZ

IPC: H01L21/48 ,  H01L23/538 ,  H01L23/498

Abstract: Embodiments disclosed herein include electronic packages and methods of making electronic packages. In an embodiment, the electronic package comprises a package substrate, an array of first level interconnect (FLI) bumps on the package substrate, wherein each FLI bump comprises a surface finish, a first pad on the package substrate, wherein the first pad comprises the surface finish, and wherein a first FLI bump of the array of FLI bumps is electrically coupled to the first pad, and a second pad on the package substrate, wherein the second pad is electrically coupled to the first pad.

公开(公告)号：US20200294920A1

公开(公告)日：2020-09-17

申请号：US16299415

申请日：2019-03-12

Applicant: Intel Corporation

Inventor： Haifa HARIRI ,  Amruthavalli P. ALUR ,  Wei-Lun K. JEN ,  Islam A. SALAMA

IPC: H01L23/538 ,  H01L23/31

Abstract: Embodiments include semiconductor packages. A semiconductor package includes a first patch and a second patch on an interposer. The semiconductor package also includes a first substrate in the first patch, and a second substrate in the second patch. The semiconductor package further includes an encapsulation layer over and around the first and second patches, a plurality of build-up layers on the first patch, the second patch, and the encapsulation layer, and a plurality of dies and a bridge on the build-up layers. The bridge may be communicatively coupled with the first substrate of the first patch and the second substrate of the second patch. The bridge may be an embedded multi-die interconnect bridge (EMIB). The first and second substrates may be EMIBs and/or high-density packaging (HDP) substrates. The bridge may be positioned between two dies, and over an edge of the first patch and an edge of the second patch.