公开(公告)号：US20190027431A1

公开(公告)日：2019-01-24

申请号：US15654399

申请日：2017-07-19

Applicant: Intel Corporation

Inventor： Hongxia FENG ,  Dingying David XU ,  Sheng C. LI ,  Matthew L. TINGEY ,  Meizi JIAO ,  Chung Kwang Christopher TAN

IPC: H01L23/498 ,  H01L23/13 ,  H01L21/48

Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.

公开(公告)号：US20240332195A1

公开(公告)日：2024-10-03

申请号：US18129879

申请日：2023-04-02

Applicant: Intel Corporation

Inventor： Naiya SOETAN-DODD ,  Srinivas V. PIETAMBARAM ,  Suddhasattwa NAD ,  Brandon C. MARIN ,  Sheng C. LI ,  Liwei CHENG

IPC: H01L23/538

CPC classification number: H01L23/5384 ,  H01L23/5381 ,  H01L23/5383 ,  H01L24/16 ,  H01L2224/16235

Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a core, where the core comprises glass. In an embodiment, a cavity is in the core, and a bridge is in the cavity. In an embodiment, the bridge comprises through substrate vias (TSVs). In an embodiment, pads are at a bottom of the cavity, where the TSVs are electrically coupled to the pads.

公开(公告)号：US20220310518A1

公开(公告)日：2022-09-29

申请号：US17213147

申请日：2021-03-25

Applicant: Intel Corporation

Inventor： Haobo CHEN ,  Xiaoying GUO ,  Hongxia FENG ,  Kristof DARMAWIKARTA ,  Bai NIE ,  Tarek A. IBRAHIM ,  Gang DUAN ,  Jeremy D. ECTON ,  Sheng C. LI ,  Leonel ARANA

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: Embodiments disclosed herein include a multi-die packages with an embedded bridge and a thinned surface. In an example, a multi-die interconnect structure includes a package substrate having a cavity. A bridge die is in the cavity of the package substrate, the bridge die including silicon. A dielectric material is over the package substrate, over the bridge die, and in the cavity. A plurality of conductive bond pads is on the dielectric material. The multi-die interconnect structure further includes a plurality of conductive pillars, individual ones of the plurality of conductive pillars on a corresponding one of the plurality of conductive bond pads. A solder resist material is on the dielectric material, on exposed portions of the plurality of conductive bond pads, and laterally surrounding the plurality of conductive pillars. The plurality of conductive pillars has a top surface above a top surface of the solder resist material.

公开(公告)号：US20200294938A1

公开(公告)日：2020-09-17

申请号：US16353164

申请日：2019-03-14

Applicant: Intel Corporation

Inventor： Rahul JAIN ,  Kyu-Oh LEE ,  Islam A. SALAMA ,  Amruthavalli P. ALUR ,  Wei-Lun K. JEN ,  Yongki MIN ,  Sheng C. LI

IPC: H01L23/64 ,  H01L23/498 ,  H01L49/02 ,  H01L23/538

Abstract: Embodiments include semiconductor packages. A semiconductor package includes a plurality of build-up layers and a plurality of conductive layers in the build-up layers. The conductive layers include a first conductive layer and a second conductive layer. The first conductive layer is over the second conductive layer and build-up layers, where a first via couples the first and second conductive layers. The semiconductor package also includes a thin film capacitor (TFC) in the build-up layers, where a second via couples the TFC to the first conductive layer, and the second via has a thickness less than a thickness of the first via. The first conductive layer may be first level interconnects. The build-up layers may be dielectrics. The TFC may include a first electrode, a second electrode, and a dielectric. The first electrode may be over the second electrode, and the dielectric may be between the first and second electrodes.

公开(公告)号：US20210327800A1

公开(公告)日：2021-10-21

申请号：US17364686

申请日：2021-06-30

Applicant: Intel Corporation

Inventor： Hongxia FENG ,  Dingying David XU ,  Sheng C. LI ,  Matthew L. TINGEY ,  Meizi JIAO ,  Chung Kwang Christopher TAN

IPC: H01L23/498 ,  H01L23/13 ,  H01L21/48 ,  H01L23/538

Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.

公开(公告)号：US20210014972A1

公开(公告)日：2021-01-14

申请号：US16505403

申请日：2019-07-08

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Tarek IBRAHIM ,  Srinivas PIETAMBARAM ,  Andrew J. BROWN ,  Gang DUAN ,  Jeremy ECTON ,  Sheng C. LI

IPC: H05K1/16 ,  H01L23/00 ,  H01F27/40 ,  H05K1/11 ,  H05K3/40 ,  H05K3/28

Abstract: Embodiments include package substrates and method of forming the package substrates. A package substrate includes a first encapsulation layer over a substrate, and a second encapsulation layer below the substrate. The package substrate also includes a first interconnect and a second interconnect vertically in the first encapsulation layer, the second encapsulation layer, and the substrate. The first interconnect includes a first plated-through-hole (PTH) core, a first via, and a second via, and the second interconnect includes a second PTH core, a third via, and a fourth via. The package substrate further includes a magnetic portion that vertically surrounds the first interconnect. The first PTH core has a top surface directly coupled to the first via, and a bottom surface directly coupled to the second via. The second PTH core has a top surface directly coupled to the third via, and a bottom surface directly coupled to the fourth via.