Invention Application
- Patent Title: MEMORY TIERING USING PCIe CONNECTED FAR MEMORY
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Application No.: US16539139Application Date: 2019-08-13
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Publication No.: US20210049101A1Publication Date: 2021-02-18
- Inventor: Anirban Ray , Paul Stonelake , Samir Mittal , Gurpreet Anand
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Main IPC: G06F12/0868
- IPC: G06F12/0868 ; G06F13/28 ; G06F3/06 ; G06F13/16 ; G06F13/42

Abstract:
A processing device in a host system monitors a data temperature of a plurality of memory pages stored in a host-addressable region of a cache memory component operatively coupled with the host system. The processing device determines that a first memory page of the plurality of memory pages satisfies a first threshold criterion pertaining to the data temperature of the first memory page and sends a first migration command indicating the first memory page to a direct memory access (DMA) engine executing on a memory-mapped storage component operatively coupled with the cache memory component and with the memory-mapped storage component via a peripheral component interconnect express (PCIe) bus. The first migration command causes the DMA engine to initiate a first DMA transfer of the first memory page from the cache memory component to a host-addressable region of the memory-mapped storage component.
Public/Granted literature
- US11379373B2 Memory tiering using PCIe connected far memory Public/Granted day:2022-07-05
Information query
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