Invention Application
- Patent Title: TIMESTAMP ALIGNMENT FOR MULTIPLE NODES
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Application No.: US17475200Application Date: 2021-09-14
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Publication No.: US20220006607A1Publication Date: 2022-01-06
- Inventor: Mark BORDOGNA , Jonathan A. ROBINSON , Srinivasan S. IYENGAR
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H04L7/00
- IPC: H04L7/00

Abstract:
Examples described herein relate to a first central processing unit (CPU) node to generate time stamp counter (TSC) values based on a first clock signal and a second CPU node to generate TSC values based on a second clock signal. In some examples, the first CPU node is to determine at least one network timer time stamp based on the TSC values based on the first clock signal and the second CPU node is to determine at least one network timer time stamp based on the TSC values based on the second clock signal. In some examples, determine at least one network timer time stamp based on the TSC values based on the first clock signal is based on (i) a relationship between the first clock signal and a network interface device main timer and (ii) a relationship between a network timer source and the network interface device main timer.
Public/Granted literature
- US12160495B2 Timestamp alignment for multiple nodes Public/Granted day:2024-12-03
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