公开(公告)号：US20230367362A1

公开(公告)日：2023-11-16

申请号：US18198150

申请日：2023-05-16

Applicant: Intel Corporation

Inventor： Mark BORDOGNA ,  Jonathan A. ROBINSON

IPC: G06F1/14 ,  H04L43/106 ,  G06F9/54 ,  G06F1/12

CPC classification number: G06F1/14 ,  H04L43/106 ,  G06F9/542 ,  G06F1/12

Abstract: Examples described herein relate to multiple processor nodes which are physically separate with interfaces to a common network interface. A local processor can run a timing recovery algorithm, and tune the master timer to align with the network domain to cause the master timer and network timing domains to be in the same domain. A common master timer can be used to align time stamps of independent processor nodes. A processor node can use the common master timer as a reference and the processor does not need to communicate with another processor to synchronize its timer.

公开(公告)号：US20220006607A1

公开(公告)日：2022-01-06

申请号：US17475200

申请日：2021-09-14

Applicant: Intel Corporation

Inventor： Mark BORDOGNA ,  Jonathan A. ROBINSON ,  Srinivasan S. IYENGAR

IPC: H04L7/00

Abstract: Examples described herein relate to a first central processing unit (CPU) node to generate time stamp counter (TSC) values based on a first clock signal and a second CPU node to generate TSC values based on a second clock signal. In some examples, the first CPU node is to determine at least one network timer time stamp based on the TSC values based on the first clock signal and the second CPU node is to determine at least one network timer time stamp based on the TSC values based on the second clock signal. In some examples, determine at least one network timer time stamp based on the TSC values based on the first clock signal is based on (i) a relationship between the first clock signal and a network interface device main timer and (ii) a relationship between a network timer source and the network interface device main timer.

公开(公告)号：US20250088342A1

公开(公告)日：2025-03-13

申请号：US18960953

申请日：2024-11-26

Applicant: Intel Corporation

Inventor： Mark BORDOGNA ,  Jonathan A. ROBINSON ,  Srinivasan S. IYENGAR

IPC: H04L7/00

Abstract: Examples described herein relate to a first central processing unit (CPU) node to generate time stamp counter (TSC) values based on a first clock signal and a second CPU node to generate TSC values based on a second clock signal. In some examples, the first CPU node is to determine at least one network timer time stamp based on the TSC values based on the first clock signal and the second CPU node is to determine at least one network timer time stamp based on the TSC values based on the second clock signal. In some examples, determine at least one network timer time stamp based on the TSC values based on the first clock signal is based on (i) a relationship between the first clock signal and a device main timer and (ii) a relationship between a network timer source and the network interface device main timer.