公开(公告)号：US20250088342A1

公开(公告)日：2025-03-13

申请号：US18960953

申请日：2024-11-26

Applicant: Intel Corporation

Inventor： Mark BORDOGNA ,  Jonathan A. ROBINSON ,  Srinivasan S. IYENGAR

IPC: H04L7/00

Abstract: Examples described herein relate to a first central processing unit (CPU) node to generate time stamp counter (TSC) values based on a first clock signal and a second CPU node to generate TSC values based on a second clock signal. In some examples, the first CPU node is to determine at least one network timer time stamp based on the TSC values based on the first clock signal and the second CPU node is to determine at least one network timer time stamp based on the TSC values based on the second clock signal. In some examples, determine at least one network timer time stamp based on the TSC values based on the first clock signal is based on (i) a relationship between the first clock signal and a device main timer and (ii) a relationship between a network timer source and the network interface device main timer.

公开(公告)号：US20230019974A1

公开(公告)日：2023-01-19

申请号：US17957719

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Srinivasan S. IYENGAR ,  Erik MCSHANE ,  Edward HO ,  Noam ELATI

IPC: G06F1/324 ,  H04L49/1546

Abstract: A network device can place some or all of the packet processing pipeline into a low-power state for detected idle intervals of sufficient duration. The network device detects idleness greater than a critical duration and automatically engages a low-power mode involving clock throttling and/or clock gating. The power savings in the packet processing pipeline in the network device is based on the average long-term residency in idleness. The idle power is reduced for the packet processing pipeline in the network device by detecting average long-term idleness as a function of the minimum latency of the packet processing pipeline, which is used to reduce the clock rate of the packet processing pipeline, thereby resulting in power savings for the network device.

公开(公告)号：US20210211214A1

公开(公告)日：2021-07-08

申请号：US17205869

申请日：2021-03-18

Applicant: Intel Corporation

Inventor： Mark BORDOGNA ,  Srinivasan S. IYENGAR

IPC: H04J3/06 ,  H04L12/26 ,  H04L29/06

Abstract: Methods and apparatus for data plane control of network time sync protocol in multi-host systems. A network interface controller (NIC) is configured to implement a network data plane that is associated with a software-based control plane implemented in the multi-host system. The NIC includes a primary timer and secondary timers at distributed endpoints such as network ports. The NIC receives network time packets having network timestamps and employs a secondary timer to associate a local timestamp with the packets. The network and local timestamps are compared by a network intellectual property block (network IP) in the data plane datapath to adjust the primary and secondary timer(s) to match the network time. The network IP uses a 2-bit wire protocol to increment and/or decrement the primary and secondary timer(s) that enables the timers to be adjusted with a nanosecond granularity.

公开(公告)号：US20250125896A1

公开(公告)日：2025-04-17

申请号：US19000227

申请日：2024-12-23

Applicant: Intel Corporation

Inventor： David R. MULVIHILL ,  Srinivasan S. IYENGAR ,  Mark BORDOGNA ,  Subrahmanya Kumar KUCHIBHOTLA

IPC: H04J3/06 ,  H04W56/00

Abstract: Examples described herein relate to a timing source. In some examples, the timing source generates a clock signal by synchronization with a second clock signal from a crystal source and subsequent synchronization with a third clock signal. In some examples, the third clock signal is synchronized to timing signals received in Ethernet packets. In some examples, the crystal source is to provide the second clock signal to the circuitry via the interface.

公开(公告)号：US20220337683A1

公开(公告)日：2022-10-20

申请号：US17500576

申请日：2021-10-13

Applicant: Intel Corporation

Inventor： Daniel Christian BIEDERMAN ,  Mark BORDOGNA ,  Srinivasan S. IYENGAR

IPC: H04L29/06

Abstract: Examples described herein relate to a network interface device that includes circuitry to determine a target time domain in which to translate a time stamp associated with a workload and identify the target time domain to cause translation of the time stamp associated with the workload to the target time domain. In some examples, the network interface device stores time domain translation parameters of time stamps from a first time domain to one or more time domains and the network interface device translates the time stamp from the first time domain to the one or more time domains. In some examples, the network interface device comprises circuitry to store time domain translation parameters of time stamps from a first time domain to one or more time domains and the server is to perform translation of the time stamp from the first time domain to the one or more time domains based on the time domain translation parameters.

公开(公告)号：US20220006607A1

公开(公告)日：2022-01-06

申请号：US17475200

申请日：2021-09-14

Applicant: Intel Corporation

Inventor： Mark BORDOGNA ,  Jonathan A. ROBINSON ,  Srinivasan S. IYENGAR

IPC: H04L7/00

Abstract: Examples described herein relate to a first central processing unit (CPU) node to generate time stamp counter (TSC) values based on a first clock signal and a second CPU node to generate TSC values based on a second clock signal. In some examples, the first CPU node is to determine at least one network timer time stamp based on the TSC values based on the first clock signal and the second CPU node is to determine at least one network timer time stamp based on the TSC values based on the second clock signal. In some examples, determine at least one network timer time stamp based on the TSC values based on the first clock signal is based on (i) a relationship between the first clock signal and a network interface device main timer and (ii) a relationship between a network timer source and the network interface device main timer.