Invention Application
- Patent Title: FABRICATING METHOD OF TRANSISTORS WITHOUT DISHING OCCURRED DURING CMP PROCESS
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Application No.: US17023391Application Date: 2020-09-17
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Publication No.: US20220084878A1Publication Date: 2022-03-17
- Inventor: Fu-Shou Tsai , Yang-Ju Lu , Yong-Yi Lin , Yu-Lung Shih , Ching-Yang Chuang , Ji-Min Lin , Kun-Ju Li
- Applicant: UNITED MICROELECTRONICS CORP.
- Applicant Address: TW Hsin-Chu City
- Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee Address: TW Hsin-Chu City
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/8234 ; H01L21/3105

Abstract:
A fabricating method of transistors includes providing a substrate with numerous transistors thereon. Each of the transistors includes a gate structure. A gap is disposed between gate structures adjacent to each other. Later, a protective layer and a first dielectric layer are formed in sequence to cover the substrate and the transistors and to fill in the gap. Next, numerous buffering particles are formed to contact the first dielectric layer. The buffering particles do not contact each other. Subsequently, a second dielectric layer is formed to cover the buffering particles. After that, a first planarization process is performed to remove part of the first dielectric layer, part of the second dielectric layer and buffering particles by taking the protective layer as a stop layer, wherein a removing rate of the second dielectric layer is greater than a removing rate of the buffering particles during the first planarization process.
Public/Granted literature
- US11257711B1 Fabricating method of transistors without dishing occurred during CMP process Public/Granted day:2022-02-22
Information query
IPC分类: