Invention Application
- Patent Title: GATE SPACING IN INTEGRATED CIRCUIT STRUCTURES
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Application No.: US17033228Application Date: 2020-09-25
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Publication No.: US20220102148A1Publication Date: 2022-03-31
- Inventor: Charles Henry Wallace , Mohit K. Haran , Paul A. Nyhus , Gurpreet Singh , Eungnak Han , David Nathan Shykind , Sean Michael Pursel
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L21/28
- IPC: H01L21/28 ; H01L27/088 ; H01L29/06 ; H01L29/423 ; H01L29/786 ; H01L21/02 ; H01L21/306 ; H01L21/308 ; H01L29/66 ; H01L21/8234
Abstract:
Discussed herein is gate spacing in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: a first gate metal having a longitudinal axis; a second gate metal, wherein the longitudinal axis of the first gate metal is aligned with a longitudinal axis of the second gate metal; a first gate contact above the first gate metal; a second gate contact above the second gate metal; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the first gate contact and the second gate contact.
Public/Granted literature
- US12002678B2 Gate spacing in integrated circuit structures Public/Granted day:2024-06-04
Information query
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