公开(公告)号：US20240096785A1

公开(公告)日：2024-03-21

申请号：US17933000

申请日：2022-09-16

申请人： Intel Corporation

发明人： June Choi ,  Charles Henry Wallace ,  Richard E. Schenker ,  Nikhil Jasvant Mehta

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L23/5226 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53242

摘要： An IC device includes a transistor, a first layer, and a second layer. The first layer is coupled to the transistors and is between the transistor and the second layer in a first direction. The first layer includes a first structure and a second structure. The first structure includes a first metal (e.g., Ru). The second structure includes a second metal (e.g., Cu). The second structure may be wrapped around by a different material that may include a third metal (e.g., Co). The first structure may be shorter than the second structure in the first direction and narrower than the second structure in a second direction orthogonal to the first direction. The first structure may be closer to the second layer than the second structure in the first direction. The first structure may be a wordline of a memory. The second structure may be a bitline.

公开(公告)号：US20220102148A1

公开(公告)日：2022-03-31

申请号：US17033228

申请日：2020-09-25

申请人： Intel Corporation

发明人： Charles Henry Wallace ,  Mohit K. Haran ,  Paul A. Nyhus ,  Gurpreet Singh ,  Eungnak Han ,  David Nathan Shykind ,  Sean Michael Pursel

IPC分类号： H01L21/28 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L29/66 ,  H01L21/8234

摘要： Discussed herein is gate spacing in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: a first gate metal having a longitudinal axis; a second gate metal, wherein the longitudinal axis of the first gate metal is aligned with a longitudinal axis of the second gate metal; a first gate contact above the first gate metal; a second gate contact above the second gate metal; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the first gate contact and the second gate contact.

公开(公告)号：US20220199420A1

公开(公告)日：2022-06-23

申请号：US17124730

申请日：2020-12-17

申请人： INTEL CORPORATION

发明人： Gurpreet Singh ,  Eungnak Han ,  Manish Chandhok ,  Richard E. Schenker ,  Florian Gstrein ,  Paul A. Nyhus ,  Charles Henry Wallace

IPC分类号： H01L21/311 ,  H01L21/768

摘要： Disclosed herein are colored gratings in microelectronic structures. For example, a microelectronic structure may include first conductive structures alternating with second conductive structures, wherein individual ones of the first conductive structures include a bottom portion and a top portion, individual cap structures are on individual ones of the second conductive structures, the bottom portions of the first conductive structures are laterally spaced apart from and aligned with the second conductive structures, and the top portions of the first conductive structures are laterally spaced apart from and aligned with the cap structures. In some embodiments, a microelectronic structure may include one or more unordered lamellar regions laterally spaced apart from and aligned with the first conductive structures.

公开(公告)号：US20220130721A1

公开(公告)日：2022-04-28

申请号：US17076870

申请日：2020-10-22

申请人： Intel Corporation

发明人： Guillaume Bouche ,  Shashi Vyas ,  Akm Shaestagir Chowdhury ,  Andy Chih-Hung Wei ,  Charles Henry Wallace

IPC分类号： H01L21/768 ,  H01L23/522

摘要： Methods for fabricating an IC structure by applying self-assembled monolayers (SAMs) are disclosed. An example IC structure includes a stack of three metallization layers provided over a support structure, where the first metallization layer includes a bottom metal line, the third metallization layer includes a top metal line, and the second metallization layer includes a via coupled between the bottom metal line and the top metal line, where via's sidewalls are enclosed by a first dielectric material. Application of one or more SAMs results in at least a portion of the via's sidewalls being lined with a second dielectric material so that the second dielectric material is between the first dielectric material and an electrically conductive material of the via, where the dielectric constant of the second dielectric material is higher than that of the first dielectric material and lower than about 6.

公开(公告)号：US11211324B2

公开(公告)日：2021-12-28

申请号：US16574308

申请日：2019-09-18

申请人： Intel Corporation

发明人： Mohit K. Haran ,  Daniel James Bahr ,  Deepak S. Rao ,  Marvin Young Paik ,  Seungdo An ,  Debashish Basu ,  Kilhyun Bang ,  Jason W. Klaus ,  Reken Patel ,  Charles Henry Wallace ,  James Jeong ,  Ruth Amy Brain

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

摘要： An example via contact patterning method includes providing a pattern of alternating trench contacts and gates over a support structure. For each pair of adjacent trench contacts and gates, a trench contact is electrically insulated from an adjacent gate by a dielectric material and/or multiple layers of different dielectric materials, and the gates are recessed with respect to the trench contacts. The method further includes wrapping a protective layer of one or more dielectric materials, and a sacrificial helmet material on top of the trench contacts to protect them during the via contact patterning and etch processes for forming via contacts over one or more gates. Such a method may advantageously allow increasing the edge placement error margin for forming via contacts of metallization stacks.

公开(公告)号：US20240203869A1

公开(公告)日：2024-06-20

申请号：US18067031

申请日：2022-12-16

申请人： Intel Corporation

发明人： Sukru Yemenicioglu ,  Leonard P. Guler ,  Nikhil Jasvant Mehta ,  Charles Henry Wallace

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L23/5226 ,  H01L21/76892 ,  H01L23/53228 ,  H01L23/53257

摘要： Methods for fabricating an integrated circuit (IC) device with one or more hybrid metal lines are provided. An example IC device includes a substrate; and a metal line extending, along an axis, over the substrate. The metal line has a first end and a second end along the axis. A portion of the metal line at the first end includes a first electrically conductive material. Another portion of the metal line includes a second electrically conductive material, where the second electrically conductive material is different from the first electrically conductive material. In some instances, the first electrically conductive material is a low-resistive, electrically conductive material, and the second electrically conductive material is a direct etch-compatible, electrically conductive material.

公开(公告)号：US11652045B2

公开(公告)日：2023-05-16

申请号：US17511656

申请日：2021-10-27

申请人： Intel Corporation

发明人： Mohit K. Haran ,  Daniel James Bahr ,  Deepak S. Rao ,  Marvin Young Paik ,  Seungdo An ,  Debashish Basu ,  Kilhyun Bang ,  Jason W. Klaus ,  Reken Patel ,  Charles Henry Wallace ,  James Jeong ,  Ruth Amy Brain

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L23/5226 ,  H01L21/76877 ,  H01L23/5283 ,  H01L23/5329

摘要： An example via contact patterning method includes providing a pattern of alternating trench contacts and gates over a support structure. For each pair of adjacent trench contacts and gates, a trench contact is electrically insulated from an adjacent gate by a dielectric material and/or multiple layers of different dielectric materials, and the gates are recessed with respect to the trench contacts. The method further includes wrapping a protective layer of one or more dielectric materials, and a sacrificial helmet material on top of the trench contacts to protect them during the via contact patterning and etch processes for forming via contacts over one or more gates. Such a method may advantageously allow increasing the edge placement error margin for forming via contacts of metallization stacks.

公开(公告)号：US20210183761A1

公开(公告)日：2021-06-17

申请号：US16713867

申请日：2019-12-13

申请人： Intel Corporation

发明人： Reken Patel ,  Mohit K. Haran ,  Jeremy J. Guttman ,  Shyam B. Kadali ,  Ruth Amy Brain ,  Seyedhamed M Barghi ,  Zhenjun Zhang ,  James Jeong ,  Robert M. Bigwood ,  Charles Henry Wallace

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L21/311

摘要： Disclosed herein are line patterning techniques for integrated circuit (IC) devices, as well as related devices and assemblies In some embodiments, a patterned line region of an IC device may include: a first conductive line; a second conductive line parallel to the first conductive line; a conductive bridge between the first conductive line and the second conductive line, wherein the conductive bridge is coplanar with the first conductive line and the second conductive line; and pitch-division artifacts.

公开(公告)号：US20210082805A1

公开(公告)日：2021-03-18

申请号：US16574308

申请日：2019-09-18

申请人： Intel Corporation

发明人： Mohit K. Haran ,  Daniel James Bahr ,  Deepak S. Rao ,  Marvin Young Paik ,  Seungdo An ,  Debashish Basu ,  Kilhyun Bang ,  Jason W. Klaus ,  Reken Patel ,  Charles Henry Wallace ,  James Jeong ,  Ruth Amy Brain

IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

摘要： An example via contact patterning method includes providing a pattern of alternating trench contacts and gates over a support structure. For each pair of adjacent trench contacts and gates, a trench contact is electrically insulated from an adjacent gate by a dielectric material and/or multiple layers of different dielectric materials, and the gates are recessed with respect to the trench contacts. The method further includes wrapping a protective layer of one or more dielectric materials, and a sacrificial helmet material on top of the trench contacts to protect them during the via contact patterning and etch processes for forming via contacts over one or more gates. Such a method may advantageously allow increasing the edge placement error margin for forming via contacts of metallization stacks.

公开(公告)号：US20240204083A1

公开(公告)日：2024-06-20

申请号：US18066307

申请日：2022-12-15

申请人： Intel Corporation

发明人： Gurpreet Singh ,  Manish Chandhok ,  Florian Gstrein ,  Charles Henry Wallace ,  Eungnak Han ,  Leonard P. Guler

IPC分类号： H01L29/66 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L29/6656 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/49816 ,  H01L24/16 ,  H01L25/0655 ,  H01L29/66545 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2924/15311

摘要： DSA-based spacers and liners can provide shorting margins for vias connected to conductive structures. Self-assembly of a diblock copolymer may be performed over a layer including conductive structures and insulative structures separating the conductive structures from each other. Spacers may be formed based on the self-assembly of the diblock copolymer. Each spacer includes an electrical insulator and is over an insulative structure. Each liner may wrap around one or more side surfaces of a spacer. Each pair of spacer and liner constitutes an insulative spacing structure that provides a shorting margin to avoid short between a via and a conductive structure not connected to the via. The insulative spacing structures may include a different electrical insulator from the insulative structures. The conductive structures may be arranged in parallel along a direction and have the same or similar heights in the direction and function as different contacts of a device.