Invention Application
- Patent Title: GALLIUM NITRIDE (GAN) THREE-DIMENSIONAL INTEGRATED CIRCUIT TECHNOLOGY
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Application No.: US17033509Application Date: 2020-09-25
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Publication No.: US20220102344A1Publication Date: 2022-03-31
- Inventor: Han Wui THEN , Marko RADOSAVLJEVIC , Pratik KOIRALA , Nicole K. THOMAS , Paul B. FISCHER , Adel A. ELSHERBINI , Tushar TALUKDAR , Johanna M. SWAN , Wilfred GOMES , Robert S. CHAU , Beomseok CHOI
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L29/40 ; H01L27/06 ; H01L29/20 ; H01L29/06 ; H01L23/538

Abstract:
Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.
Information query
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