公开(公告)号：US20250070083A1

公开(公告)日：2025-02-27

申请号：US18942054

申请日：2024-11-08

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Henning BRAUNISCH ,  Aleksandar ALEKSOV ,  Shawna M. LIFF ,  Johanna M. SWAN ,  Patrick MORROW ,  Kimin JUN ,  Brennen MUELLER ,  Paul B. FISCHER

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/00

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.

公开(公告)号：US20250040231A1

公开(公告)日：2025-01-30

申请号：US18914863

申请日：2024-10-14

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Pratik KOIRALA ,  Nicole K. THOMAS ,  Paul B. FISCHER ,  Adel A. ELSHERBINI ,  Tushar TALUKDAR ,  Johanna M. SWAN ,  Wilfred GOMES ,  Robert S. CHAU ,  Beomseok CHOI

IPC: H01L27/06 ,  H01L21/765 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/64 ,  H01L25/00 ,  H01L25/065 ,  H01L27/092 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778 ,  H01L29/786

Abstract: Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.

公开(公告)号：US20190006296A1

公开(公告)日：2019-01-03

申请号：US15749026

申请日：2015-09-27

Applicant: Intel Corporation

Inventor： Patrick MORROW ,  Paul B. FISCHER

IPC: H01L23/64 ,  H01L49/02 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/645 ,  H01L21/845 ,  H01L23/5384 ,  H01L24/16 ,  H01L25/0657 ,  H01L27/1211 ,  H01L28/00 ,  H01L28/10 ,  H01L2924/1206

Abstract: An apparatus and a system including an apparatus including a circuit structure including a device stratum including a plurality of transistor devices each including a first side and an opposite second side; an inductor disposed on the second side of the structure; and a contact coupled to the inductor and routed through the device stratum and coupled to at least one of the plurality of transistor devices on the first side. A method including forming a plurality of transistor devices on a substrate, the plurality of transistor devices defining a device stratum including a first side and an opposite second side, wherein the second side is coupled to the substrate; removing a portion of the substrate; forming at least one inductor on the second side of the device stratum; and coupling the at least one inductor to at least one of the plurality of transistor devices.

公开(公告)号：US20220254754A1

公开(公告)日：2022-08-11

申请号：US17728813

申请日：2022-04-25

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Henning BRAUNISCH ,  Aleksandar ALEKSOV ,  Shawna M. LIFF ,  Johanna M. SWAN ,  Patrick MORROW ,  Kimin JUN ,  Brennen MUELLER ,  Paul B. FISCHER

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/00

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.

公开(公告)号：US20200227396A1

公开(公告)日：2020-07-16

申请号：US15754822

申请日：2015-09-24

Applicant: Intel Corporation

Inventor： Sansaptak W. DASGUPTA ,  Marko RADOSAVLJEVIC ,  Han Wui THEN ,  Ravi PILLARISETTY ,  Kimin JUN ,  Patrick MORROW ,  Valluri R. RAO ,  Paul B. FISCHER ,  Robert S. CHAU

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L21/78 ,  H01L25/00

Abstract: The electrical and electrochemical properties of various semiconductors may limit the usefulness of various semiconductor materials for one or more purposes. A completed gallium nitride (GaN) semiconductor layer containing a number of GaN power management integrated circuit (PMIC) dies may be bonded to a completed silicon semiconductor layer containing a number of complementary metal oxide (CMOS) control circuit dies. The completed GaN layer and the completed silicon layer may be full size (e.g., 300 mm). A layer transfer operation may be used to bond the completed GaN layer to the completed silicon layer. The layer transfer operation may be performed on full size wafers. After slicing the full size wafers a large number of multi-layer dies, each having a GaN die layer transferred to a silicon die may be produced.

公开(公告)号：US20190287935A1

公开(公告)日：2019-09-19

申请号：US16345627

申请日：2016-12-21

Applicant: Intel Corporation

Inventor： Paul B. FISCHER ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA

IPC: H01L23/66 ,  H01L23/14 ,  H01L23/13 ,  H01L23/522 ,  H01L21/50

Abstract: Embodiments of the invention include a microelectronic device that includes an insulating substrate, a RF transistor layer, and an interconnect structure disposed on the RF transistor layer. The RF transistor layer includes RF transistors for microwave frequencies. The interconnect structure includes at least one layer of dielectric material and a conductive layer having a plurality of conductive lines. The insulating substrate reduces parasitic capacitances and parasitic coupling to the insulating substrate.

公开(公告)号：US20230081460A1

公开(公告)日：2023-03-16

申请号：US17476310

申请日：2021-09-15

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Nicole K. THOMAS ,  Pratik KOIRALA ,  Nityan NAIR ,  Paul B. FISCHER

IPC: G02B6/42 ,  G06F1/16

Abstract: Gallium nitride (GaN) integrated circuit technology with optical communication is described. In an example, an integrated circuit structure includes a layer or substrate having a first region and a second region, the layer or substrate including gallium and nitrogen. A GaN-based device is in or on the first region of the layer or substrate. A CMOS-based device is over the second region of the layer or substrate. An interconnect structure is over the GaN-based device and over the CMOS-based device, the interconnect structure including conductive interconnects and vias in a dielectric layer. A photonics waveguide is over the interconnect structure, the photonics waveguide including silicon, and the photonics waveguide bonded to the dielectric layer of the interconnect structure.

公开(公告)号：US20220093683A1

公开(公告)日：2022-03-24

申请号：US17031719

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Ibrahim BAN ,  Paul B. FISCHER ,  Kimin JUN ,  Paul NORDEEN ,  Pratik KOIRALA ,  Tushar TALUKDAR

IPC: H01L27/20 ,  H01L29/16 ,  H01L29/20 ,  H03H9/02 ,  H03H9/17 ,  H03H9/54 ,  H03H9/56

Abstract: Embodiments disclosed herein include resonators and methods of forming such resonators. In an embodiment a resonator comprises a substrate, where a cavity is disposed into a surface of the substrate, and a piezoelectric film suspended over the cavity. In an embodiment, the piezoelectric film has a first surface and a second surface opposite from the first surface, and the piezoelectric film is single crystalline and has a thickness that is 0.5 μm or less. In an embodiment a first electrode is over the first surface of the piezoelectric film, and a second electrode is over the second surface of the piezoelectric film.

公开(公告)号：US20200266278A1

公开(公告)日：2020-08-20

申请号：US16279150

申请日：2019-02-19

Applicant: INTEL CORPORATION

Inventor： Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA ,  Han Wui THEN ,  Paul B. FISCHER ,  Walid M. HAFEZ

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/778 ,  H01L21/765 ,  H01L21/28 ,  H01L29/66 ,  H01L23/66

Abstract: A semiconductor device structure having a “T-shaped” gate structure is described. A narrower first portion supports high frequency processes (e.g., gigahertz wireless communications). A second portion of the gate structure has a second width greater than the first width. Lateral extensions (sometimes referred to as “field plates), thinner and wider than the second portion, extend from the second portion. This combination of a gate structure having a narrow first portion and a wider second portion improves the performance of the semiconductor device in applications that involve both high frequency and high power consumption.

公开(公告)号：US20180233409A1

公开(公告)日：2018-08-16

申请号：US15753124

申请日：2015-09-24

Applicant: Intel Corporation

Inventor： Il-Seok SON ,  Colin T. CARVER ,  Paul B. FISCHER ,  Patrick MORROW ,  Kimin JUN

IPC: H01L21/768 ,  H01L27/088 ,  H01L29/06 ,  H01L21/306 ,  H01L21/304 ,  H01L21/84 ,  H01L25/065

CPC classification number: H01L21/76898 ,  H01L21/304 ,  H01L21/30608 ,  H01L21/30625 ,  H01L21/84 ,  H01L21/845 ,  H01L25/0657 ,  H01L27/0886 ,  H01L29/0649

Abstract: Embodiments of the present disclosure describe techniques for revealing a backside of an integrated circuit (IC) device, and associated configurations. The IC device may include a plurality of fins formed on a semiconductor substrate (e.g., silicon substrate), and an isolation oxide may be disposed between the fins along the backside of the IC device. A portion of the semiconductor substrate may be removed to leave a remaining portion. The remaining portion may be removed by chemical mechanical planarization (CMP) using a selective slurry to reveal the backside of the IC device. Other embodiments may be described and/or claimed.