公开(公告)号：US20240224536A1

公开(公告)日：2024-07-04

申请号：US18090807

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Tahir GHANI ,  Jack T. KAVALIEROS ,  Anand S. MURTHY ,  Wilfred GOMES

IPC: H10B51/30

CPC classification number: H10B51/30

Abstract: Structures having layer select transistors for shared peripherals in memory are described. In an example, an integrated circuit structure includes a memory structure layer including a capacitor array coupled to a plurality of plate lines. A memory transistor layer is beneath the memory structure layer, the memory transistor layer including front end transistors coupled to corresponding capacitors of the capacitor array of the memory structure layer. A select transistor layer is over the memory structure layer, the select transistor layer including backend transistors having a channel composition different than the front end transistors. One or more of the backend transistors is coupled to one or more of the plurality of plate lines of the memory structure layer.

公开(公告)号：US20240222520A1

公开(公告)日：2024-07-04

申请号：US18090822

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Sagar SUTHRAM ,  Wilfred GOMES ,  Tahir GHANI ,  Anand S. MURTHY ,  Pushkar RANADE

IPC: H01L29/786 ,  H01L23/48 ,  H01L27/088 ,  H01L29/06 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

CPC classification number: H01L29/78696 ,  H01L23/481 ,  H01L27/0886 ,  H01L29/0673 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: Structures having vertical shared gate high-drive thin film transistors are described. In an example, an integrated circuit structure includes a stack of alternating dielectric layers and metal layers. A trench is through the stack of alternating dielectric layers and metal layers. A semiconductor channel layer is along sides of the trench. A gate dielectric layer is along sides the semiconductor channel layer in the trench. A gate electrode is within sides of the gate dielectric layer.

公开(公告)号：US20240222271A1

公开(公告)日：2024-07-04

申请号：US18090828

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Pushkar RANADE ,  Wilfred GOMES ,  Tahir GHANI ,  Anand S. MURTHY ,  Sagar SUTHRAM

IPC: H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L23/528 ,  H01L27/0922 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: Structures having routing across layers of channel structures are described. In an example, an integrated circuit structure includes a first stack of horizontal nanowires along a vertical direction. A second stack of horizontal nanowires is along the vertical direction, the second stack of horizontal nanowires beneath the first stack of horizontal nanowires. A conductive routing layer extends laterally between the first stack of horizontal nanowires and the second stack of horizontal nanowires.

公开(公告)号：US20230420533A1

公开(公告)日：2023-12-28

申请号：US17851960

申请日：2022-06-28

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Wilfred GOMES ,  Anand S. MURTHY ,  Tahir GHANI ,  Sagar SUTHRAM

IPC: H01L29/423 ,  H01L27/12 ,  H01L27/092 ,  H01L23/528 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L27/1203 ,  H01L27/092 ,  H01L23/528 ,  H01L29/401 ,  H01L29/66439 ,  H01L29/66742

Abstract: Structures having AOI gates with routing across nanowires are described. In an example, an integrated circuit structure includes a stack of horizontal nanowires along a vertical direction. A gate stack is over the stack of horizontal nanowires and is surrounding a channel region of each of the horizontal nanowires, the gate stack having one or more cuts in the vertical direction.

公开(公告)号：US20200258852A1

公开(公告)日：2020-08-13

申请号：US16635536

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Wilfred GOMES ,  Mark BOHR ,  Doug INGERLY ,  Rajesh KUMAR ,  Harish KRISHNAMURTHY ,  Nachiket Venkappayya DESAI

IPC: H01L23/64 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: Techniques and mechanisms for providing an inductor with an integrated circuit (IC) die. In an embodiment, the IC die comprises integrated circuitry and one or more first metallization layers. The IC die is configured to couple to a circuit device including one or more second metallization layers, where such coupling results in the formation of an inductor which is coupled to the integrated circuitry. One or more loop structures of the inductor each span both some or all of the one or more first metallization layers and some or all of the one or more second metallization layers. In another embodiment, the IC die or the circuit device includes a ferromagnetic material to concentrate a magnetic flux which is provided with the inductor.

公开(公告)号：US20250040231A1

公开(公告)日：2025-01-30

申请号：US18914863

申请日：2024-10-14

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Pratik KOIRALA ,  Nicole K. THOMAS ,  Paul B. FISCHER ,  Adel A. ELSHERBINI ,  Tushar TALUKDAR ,  Johanna M. SWAN ,  Wilfred GOMES ,  Robert S. CHAU ,  Beomseok CHOI

IPC: H01L27/06 ,  H01L21/765 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/64 ,  H01L25/00 ,  H01L25/065 ,  H01L27/092 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778 ,  H01L29/786

Abstract: Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.

公开(公告)号：US20240222276A1

公开(公告)日：2024-07-04

申请号：US18089877

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Sagar SUTHRAM ,  Pushkar RANADE ,  Tahir GHANI ,  Anand S. MURTHY ,  Wilfred GOMES

IPC: H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H05K1/18

CPC classification number: H01L23/5286 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H05K1/181 ,  H05K2201/10159

Abstract: Structures having lookup table decoders for FPGAs with high DRAM transistor density are described. In an example, an integrated circuit structure includes a plurality of fins or nanowire stacks, individual ones of the plurality of fins or nanowire stacks having a longest dimension along a first direction. A plurality of gate structures is over the plurality of fins or nanowire stacks, individual ones of the plurality of gate structures having a longest dimension along a second direction, wherein the first direction is non-orthogonal to the second direction.

公开(公告)号：US20240221821A1

公开(公告)日：2024-07-04

申请号：US18089886

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Wilfred GOMES ,  Tahir GHANI ,  Anand S. MURTHY

IPC: G11C11/409 ,  H01L23/522 ,  H01L23/528

CPC classification number: G11C11/409 ,  H01L23/5226 ,  H01L23/5283

Abstract: Structures having two-transistor gain cell are described. In an example, an integrated circuit structure includes a frontend device layer including a read transistor. A backend device layer is above the frontend device layer, the backend device layer including a write transistor. An intervening interconnect layer is between the backend device layer and the frontend device layer, the intervening interconnect layer coupling the write transistor of the backend device layer to the read transistor of the front-end device layer.

公开(公告)号：US20240103304A1

公开(公告)日：2024-03-28

申请号：US17954286

申请日：2022-09-27

Applicant: Intel Corporation

Inventor： Sagar SUTHRAM ,  John HECK ,  Ling LIAO ,  Mengyuan HUANG ,  Wilfred GOMES ,  Pushkar RANADE ,  Abhishek Anil SHARMA

IPC: G02F1/025

CPC classification number: G02F1/025

Abstract: Embodiments disclosed herein include a photonics module and methods of forming photonics modules. In an embodiment, the photonics module comprises a waveguide, and a modulator adjacent to the waveguide. In an embodiment, the modulator comprises a PN junction with a P-doped region and an N-doped region, where the PN junction is vertically oriented so that the P-doped region is over the N-doped region.

公开(公告)号：US20240103216A1

公开(公告)日：2024-03-28

申请号：US17954292

申请日：2022-09-27

Applicant: Intel Corporation

Inventor： Sagar SUTHRAM ,  John HECK ,  Ling LIAO ,  Mengyuan HUANG ,  Wilfred GOMES ,  Pushkar RANADE ,  Abhishek Anil SHARMA

IPC: G02B6/12 ,  H01L25/16

CPC classification number: G02B6/12004 ,  H01L25/167

Abstract: Embodiments disclosed herein include through silicon waveguides and methods of forming such waveguides. In an embodiment, a through silicon waveguide comprises a substrate, where the substrate comprises silicon. In an embodiment, a waveguide is provided through the substrate. In an embodiment, the waveguide comprises a waveguide structure. and a cladding around the waveguide structure.