Invention Application
- Patent Title: LOW RESISTANCE APPROACHES FOR FABRICATING CONTACTS AND THE RESULTING STRUCTURES
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Application No.: US17033471Application Date: 2020-09-25
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Publication No.: US20220102521A1Publication Date: 2022-03-31
- Inventor: Gilbert DEWEY , Nazila HARATIPOUR , Siddharth CHOUKSEY , Jack T. KAVALIEROS , Jitendra Kumar JHA , Matthew V. METZ , Mengcheng LU , Anand S. MURTHY , Koustav GANGULY , Ryan KEECH , Glenn A. GLASS , Arnab SEN GUPTA
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L29/45
- IPC: H01L29/45 ; H01L29/06 ; H01L29/417 ; H01L29/423 ; H01L29/786 ; H01L29/08 ; H01L29/78 ; H01L21/285 ; H01L29/66

Abstract:
Low resistance approaches for fabricating contacts, and semiconductor structures having low resistance metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor structure above a substrate. A gate electrode is over the semiconductor structure, the gate electrode defining a channel region in the semiconductor structure. A first semiconductor source or drain structure is at a first end of the channel region at a first side of the gate electrode. A second semiconductor source or drain structure is at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end. A source or drain contact is directly on the first or second semiconductor source or drain structure, the source or drain contact including a barrier layer and an inner conductive structure.
Public/Granted literature
- US12119387B2 Low resistance approaches for fabricating contacts and the resulting structures Public/Granted day:2024-10-15
Information query
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