An apparatus is described. The apparatus includes a memory controller having a network interface and a channel interface. The channel interface is to send read, write and refresh commands into a region of a memory. The network interface is to receive memory access requests from a network, wherein the memory requests target the region of the memory. The memory requests are sent into the network by one or more host interfaces. The memory controller has bank refresh logic circuitry. The memory controller has signaling logic circuitry to send a back pressure signal to the one or more host interfaces. The back pressure signal identifies a bank of the region of the memory that is about to be refreshed by the bank refresh logic circuitry. The back pressure signal is to inform the one or more host interfaces that any memory requests that target the bank will not be serviced by the region of memory before the bank begins to be refreshed.