公开(公告)号：US20230385208A1

公开(公告)日：2023-11-30

申请号：US18232765

申请日：2023-08-10

Applicant: Intel Corporation

Inventor： Saravanan SETHURAMAN ,  Tonia M. ROSE

IPC: G06F13/16 ,  G06F13/36

CPC classification number: G06F13/1668 ,  G06F13/36

Abstract: A configuration register update mode can be implemented as a register word update (RWUPD) mode for a registering clock driver (RCD) or as a mode register update (MRUPD) mode for a dynamic random access memory (DRAM) device. In the update mode, In the update mode, the memory device (either the RCD or the DRAM) can perform configuration of any number of configuration registers with in-band register writes. The in-band register writes can be used to configure decision feedback equalization (DFE) settings, as well as other configuration settings for non-DFE configurations of a memory device interface.

公开(公告)号：US20250117343A1

公开(公告)日：2025-04-10

申请号：US18990908

申请日：2024-12-20

Applicant: Intel Corporation

Inventor： Saravanan SETHURAMAN ,  George VERGIS

IPC: G06F13/16

Abstract: A system includes a memory die stack that provides sensing information via proxy. The memory die stack includes at least a first memory die with a sensor that generates sensing data for the first memory die and a second memory die with a sensor that generates sensing data for the second memory die. The proxy is a logic device that aggregates and sends the sensing data for both memory dies over a management communication bus.

公开(公告)号：US20240320347A1

公开(公告)日：2024-09-26

申请号：US18679060

申请日：2024-05-30

Applicant: Intel Corporation

Inventor： Saravanan SETHURAMAN ,  George VERGIS

IPC: G06F21/60

CPC classification number: G06F21/602 ,  G06F21/606

Abstract: A memory subsystem allows the memory controller and the memory to create a trusted communication channel based on a certificate exchange. The memory and memory controller have a key storage to store the certificates. The memory controller can be restricted to only be enabled to access a system data storage array after the trusted communication channel is established.

公开(公告)号：US20240249795A1

公开(公告)日：2024-07-25

申请号：US18622900

申请日：2024-03-30

Applicant: Intel Corporation

Inventor： Saravanan SETHURAMAN ,  Tonia M. ROSE

IPC: G11C29/56

CPC classification number: G11C29/56004 ,  G11C29/56012 ,  G11C29/56016

Abstract: A configuration register update mode can be implemented as an MRUPD (mode register update) mode for a DRAM (dynamic random access memory) device. In one example, the MRUPD can also be applied to update an RCD (registering clock driver). In the update mode, the memory device (either the RCD or the DRAM) can perform configuration of any number of configuration registers with in-band register writes. The in-band register writes can be used to configure DFE (decision feedback equalization) settings, as well as other configuration settings for non-DFE configurations of a memory device interface.

公开(公告)号：US20230136268A1

公开(公告)日：2023-05-04

申请号：US18086634

申请日：2022-12-21

Applicant: Intel Corporation

Inventor： Saravanan SETHURAMAN ,  Tonia M. ROSE ,  John V. LOVELACE ,  George VERGIS

IPC: G06F3/06

Abstract: An apparatus is described. The apparatus includes data buffer to memory chip write training circuitry. The data buffer to memory chip write training circuitry to send MDQ/MDQS phase relationship programming information, write commands and read commands to the data buffer chips for multiple write training iterations without a host memory controller having provided the MDQ/MDQS phase relationship programming information, the write commands and the read commands to the data buffer to memory chip write training circuitry.

公开(公告)号：US20220301608A1

公开(公告)日：2022-09-22

申请号：US17830118

申请日：2022-06-01

Applicant: Intel Corporation

Inventor： Saravanan SETHURAMAN ,  Tonia M. ROSE ,  George VERGIS ,  John V. LOVELACE

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/18

Abstract: An apparatus is described. The apparatus includes a register clock redriver (RCD) chip comprising a buffer communication (BCOM) interface, a BCOM training control circuit and BCOM training control register space, the BCOM training control circuit is to: transmit a series of symbol transmissions over the BCOM interface to a data buffer with different respective clock phase delays to sweep the symbol transmissions within an eye window; collect resultants of the symbol transmissions from the data buffer; and, perform an analysis on the resultants to determine an appropriate clock phase within the eye window.

公开(公告)号：US20220276958A1

公开(公告)日：2022-09-01

申请号：US17747950

申请日：2022-05-18

Applicant: Intel Corporation

Inventor： Saravanan SETHURAMAN ,  George VERGIS ,  Tonia M. ROSE ,  John R. GOLES ,  John V. LOVELACE

IPC: G06F12/06

Abstract: A memory chip is described. The memory chip includes self identification circuitry to self identify the memory chip. The self identification circuitry is to determine a resistance of a resistor and correlate the memory chip's identity to the resistance. A registering clock driver (RCD) chip is described. The RCD chip includes a controller. The controller is to receive provisional IDs (PIDs) from memory chips on a same memory module as the RCD chip. The controller is to program the memory chips with respective logical IDs (LIDs) based on a correlation of the PIDs and the LIDs.

公开(公告)号：US20220011960A1

公开(公告)日：2022-01-13

申请号：US17485343

申请日：2021-09-25

Applicant: Intel Corporation

Inventor： Chang Kian TAN ,  Ru Yin NG ,  Saravanan SETHURAMAN ,  Kuljit S. BAINS

IPC: G06F3/06

Abstract: Per channel thermal management techniques are described herein. In one example, a memory controller receives channel temperature information for one or more channels of one or more dies in the stack. The memory controller can then throttle commands at a channel-level based on the channel temperature information. In one example, row commands and column commands to a channel are throttled at independent rates based on the channel temperature information. In one example, a row command throttling rate or column command throttling rate is based on a ratio of alternating on-time to off time of throttling signals, or a window of time in which commands are enabled or disabled to a channel. In one example, the row and column command throttling signals can be staggered across channels or pseudo channels.

公开(公告)号：US20230017161A1

公开(公告)日：2023-01-19

申请号：US17950663

申请日：2022-09-22

Applicant: Intel Corporation

Inventor： Saravanan SETHURAMAN ,  Tonia M. ROSE ,  George VERGIS ,  John V. LOVELACE

IPC: G11C7/10 ,  G11C8/18

Abstract: System boot time is decreased by performing Memory Receive enable (MRE) training and MDQ-MDQS Read Delay (MRD) training on a buffered Dual In-Line Memory Module (DIMM). MRE training configures the time at which a data buffer on the buffered DIMM enables its receivers to capture data read from DRAM integrated circuits on a MDQ/MDQS bus between the DRAM and the data buffer on the DIMM. After the MRE training has completed, the data buffer is configured to enable the data buffer receivers to receive data on the MDQ bus on the buffered DIMM during the preamble of the incoming MDQS burst from a read transaction in the DRAM. MRD training tunes the relationship between the MDQ/MDQS bus to ensure sufficient setup and hold eye margins for MDQ so that the data buffer optimally samples the data driven by the DRAM during reads of the DRAM.

公开(公告)号：US20220300197A1

公开(公告)日：2022-09-22

申请号：US17749916

申请日：2022-05-20

Applicant: Intel Corporation

Inventor： Saravanan SETHURAMAN ,  Tonia M. ROSE ,  George VERGIS ,  John V. LOVELACE

IPC: G06F3/06

Abstract: Autonomous QCS and QCA training by the RCD can remove host intervention, freeing the host to handle other tasks while the RCD trains the backside CS and CA buses. In one example, the RCD autonomously trains QCS and/or QCA signal lines by triggering the DRAMs entry into a training mode, driving the signal lines with patterns, and sweeping through delay values for the signal lines. The RCD receives training feedback from the DRAMs over a sideband bus (such as an I3C bus) and programs a delay for the one or more signal lines based on the training feedback. Thus, autonomous QCS and QCA training can reduce training time for every boot by removing host intervention and saving hose cycles.