Invention Application
- Patent Title: CHIPLET FIRST ARCHITECTURE FOR DIE TILING APPLICATIONS
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Application No.: US17556667Application Date: 2021-12-20
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Publication No.: US20220115334A1Publication Date: 2022-04-14
- Inventor: Srinivas PIETAMBARAM , Gang DUAN , Deepak KULKARNI , Rahul MANEPALLI , Xiaoying GUO
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L21/48 ; H01L21/56 ; H01L23/31 ; H01L23/538

Abstract:
Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.
Public/Granted literature
- US11973041B2 Chiplet first architecture for die tiling applications Public/Granted day:2024-04-30
Information query
IPC分类: