公开(公告)号：US20240243088A1

公开(公告)日：2024-07-18

申请号：US18622486

申请日：2024-03-29

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Jung Kyu HAN ,  Thomas HEATON ,  Ali LEHAF ,  Rahul MANEPALLI ,  Srinivas PIETAMBARAM ,  Jacob VEHONSKY

IPC: H01L23/00 ,  C25D3/38 ,  C25D5/02 ,  C25D7/12

CPC classification number: H01L24/14 ,  C25D3/38 ,  C25D5/022 ,  C25D7/12 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/1111 ,  H01L2224/11462 ,  H01L2224/13147 ,  H01L2224/1403

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to manufacturing a package having a substrate with a first side and a second side opposite the first side, where a copper layer is coupled with a first region of the first side of the substrate and includes a plurality of bumps coupled with the first region of the first side of the substrate where one or more second regions on the first side of the substrate not coupled with a copper layer, and where a layout of the one or more second regions on the first side of the substrate is to vary a growth, respectively, of each of the plurality of bumps during a plating process by modifying a local copper density of each of the plurality of bumps.

公开(公告)号：US20190393183A1

公开(公告)日：2019-12-26

申请号：US16017393

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Suddhasattwa NAD ,  Rahul MANEPALLI ,  Marcel WALL

IPC: H01L23/00 ,  H01L23/29 ,  H01L21/48 ,  H01L21/56

Abstract: Embodiments include a package substrate, a method of forming the package substrate, and a self-assembled monolayers (SAM) layer. The package substrate includes a SAM layer on portions of a conductive pad, where the SAM layer includes alight-reflective moieties. The package substrate also includes a via on a surface portion of the conductive pad, and a dielectric on and around the via, the SAM layer, and the conductive pad, where the SAM layer surrounds and contacts a surface of the via. The SAM layer may be an interfacial organic layer. The light-reflective moieties may include a hemicyanine, a cyclic-hemicyanine, an oligothiophene, and/or a conjugated aromatic compound. The SAM layer may include a molecular structure having a first end group of a first monolayer, an intermediate group, a fifth end group of a second monolayer, and one or more of a first and second light-reflective moieties.

公开(公告)号：US20240188222A1

公开(公告)日：2024-06-06

申请号：US18060595

申请日：2022-12-01

Applicant: Intel Corporation

Inventor： Rahul MANEPALLI ,  Srinivas PIETAMBARAM ,  Darko GRUJICIC ,  Marcel WALL ,  Jason STEILL

IPC: H05K3/22 ,  H05K1/03 ,  H05K1/11 ,  H05K3/00

CPC classification number: H05K3/225 ,  H05K1/0306 ,  H05K1/115 ,  H05K3/002 ,  H05K3/0029 ,  H01L21/486

Abstract: The present disclosure is directed to a method providing a substrate core having a glass core layer with top and bottom surfaces and a build-up process performing operations to form a plurality of through-glass vias formed through the glass core layer and a plurality of conductive layers on the top and bottom surfaces of the glass core layer. As an integral part of the build-up process, a defect detection method may be used to detect defects in the glass core layer. The inspection for defects may be performed after selected operations. After one or more defect (e.g., crack) is uncovered, a repair process may be performed to repair the defects in the glass core layer. The repair of a defect may be performed immediately upon detection or after selected operations as a comprehensive repair of a group of defects.

公开(公告)号：US20230361044A1

公开(公告)日：2023-11-09

申请号：US18224794

申请日：2023-07-21

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Rahul MANEPALLI ,  Gang DUAN

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/5381 ,  H01L23/5386 ,  H01L23/3107 ,  H01L23/562 ,  H01L25/0652 ,  H01L25/50 ,  H01L21/6835 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/5384 ,  H01L2225/06589 ,  H01L2221/68372 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06582

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, a microelectronic device package may include a redistribution layer (RDL) and an interposer over the RDL. In an embodiment, a glass core may be formed over the RDL and surround the interposer. In an embodiment, the microelectronic device package may further comprise a plurality of dies over the interposer. In an embodiment, the plurality of dies are communicatively coupled with the interposer.

公开(公告)号：US20220010452A1

公开(公告)日：2022-01-13

申请号：US17482513

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Chandrasekharan NAIR ,  Darko GRUJICIC ,  Rengarajan SHANMUGAM ,  Srinivasan RAMAN ,  Roy DITTLER ,  Daniel SOWA ,  Robert BARESEL, II ,  Marcel WALL ,  Rahul MANEPALLI

IPC: C25D17/06 ,  C25D17/12 ,  C25D17/00 ,  H01L21/67

Abstract: The present disclosure is directed to an electroless plating process using a panel basket for holding semiconductor panels comprising a plurality of metal pads and shielding the metal pads from contaminants and over-etching and under-etching caused by the contaminants.

公开(公告)号：US20200312698A1

公开(公告)日：2020-10-01

申请号：US16363426

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Suddhasattwa NAD ,  Rahul MANEPALLI

IPC: H01L21/683 ,  H01L23/538 ,  H01L25/065

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a package substrate having a first surface and a second surface opposite from the first surface, and a monolayer having a plurality of first molecules over the first surface of the package substrate. In an embodiment, the first molecules each comprise a first functional group attached to the first surface, and a first release moiety attached to the first functional group.

公开(公告)号：US20250015003A1

公开(公告)日：2025-01-09

申请号：US18887990

申请日：2024-09-17

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Rahul MANEPALLI ,  Gang DUAN

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, a microelectronic device package may include a redistribution layer (RDL) and an interposer over the RDL. In an embodiment, a glass core may be formed over the RDL and surround the interposer. In an embodiment, the microelectronic device package may further comprise a plurality of dies over the interposer. In an embodiment, the plurality of dies are communicatively coupled with the interposer.

公开(公告)号：US20220254721A1

公开(公告)日：2022-08-11

申请号：US17732365

申请日：2022-04-28

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Rahul MANEPALLI ,  Gang DUAN

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, a microelectronic device package may include a redistribution layer (RDL) and an interposer over the RDL. In an embodiment, a glass core may be formed over the RDL and surround the interposer. In an embodiment, the microelectronic device package may further comprise a plurality of dies over the interposer. In an embodiment, the plurality of dies are communicatively coupled with the interposer.

公开(公告)号：US20220238458A1

公开(公告)日：2022-07-28

申请号：US17716947

申请日：2022-04-08

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Gang DUAN ,  Deepak KULKARNI ,  Rahul MANEPALLI ,  Xiaoying GUO

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.

公开(公告)号：US20200312771A1

公开(公告)日：2020-10-01

申请号：US16366661

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Bai NIE ,  Gang DUAN ,  Srinivas PIETAMBARAM ,  Jesse JONES ,  Yosuke KANAOKA ,  Hongxia FENG ,  Dingying XU ,  Rahul MANEPALLI ,  Sameer PAITAL ,  Kristof DARMAWIKARTA ,  Yonggang LI ,  Meizi JIAO ,  Chong ZHANG ,  Matthew TINGEY ,  Jung Kyu HAN ,  Haobo CHEN

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.