Invention Application
- Patent Title: GRAPHICS PROCESSOR OPERATION SCHEDULING FOR DETERMINISTIC LATENCY
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Application No.: US17428216Application Date: 2020-03-14
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Publication No.: US20220122215A1Publication Date: 2022-04-21
- Inventor: JOYDEEP RAY , SELVAKUMAR PANNEER , SAURABH TANGRI , BEN ASHBAUGH , SCOTT JANUS , ABHISHEK APPU , VARGHESE GEORGE , RAVISHANKAR IYER , NILESH JAIN , PATTABHIRAMAN K , ALTUG KOKER , MIKE MACPHERSON , JOSH MASTRONARDE , ELMOUSTAPHA OULD-AHMED-VALL , JAYAKRISHNA P. S , ERIC SAMSON
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- International Application: PCT/US20/22839 WO 20200314
- Main IPC: G06T1/60
- IPC: G06T1/60 ; G06F12/06 ; G06F12/1009 ; G06T1/20 ; G06F12/0875 ; G06F9/38

Abstract:
Embodiments described herein include software, firmware, and hardware that provides techniques to enable deterministic scheduling across multiple general-purpose graphics processing units. One embodiment provides a multi-GPU architecture with uniform latency. One embodiment provides techniques to distribute memory output based on memory chip thermals. One embodiment provides techniques to enable thermally aware workload scheduling. One embodiment provides techniques to enable end to end contracts for workload scheduling on multiple GPUs.
Public/Granted literature
- US12079155B2 Graphics processor operation scheduling for deterministic latency Public/Granted day:2024-09-03
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