-
公开(公告)号：US20200211261A1
公开(公告)日：2020-07-02
申请号：US16235744
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： SCOTT JANUS , PRASOONKUMAR SURTI , KARTHIK VAIDYANATHAN , GABOR LIKTOR , CARSTEN BENTHIN , PHILIP LAWS
Abstract: Apparatus and method for general ray tracing queries. For example, one embodiment of an apparatus comprises: a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes associated with a graphics scene; traversal/intersection hardware logic to traverse one or more rays through the acceleration data structure to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; shape processing hardware logic to specify three dimensional (3D) shape data indicating one or more 3D shapes to be used to perform queries with respect to the hierarchical acceleration data structure; query processing hardware logic to execute queries comprising comparisons between nodes of the hierarchical acceleration data structure and the 3D shape data to generate a result indicating overlap between the 3D shapes and the nodes.
-
公开(公告)号：US20200211252A1
公开(公告)日：2020-07-02
申请号：US16235893
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： PRASOONKUMAR SURTI , CARSTEN BENTHIN , KARTHIK VAIDYANATHAN , PHILIP LAWS , SCOTT JANUS , SVEN WOOP
Abstract: Cluster of acceleration engines to accelerate intersections. For example, one embodiment of an apparatus comprises: a set of graphics cores to execute a first set of instructions of a primary graphics thread; a scalar cluster comprising a plurality of scalar execution engines; and a communication fabric interconnecting the set of graphics cores and the scalar cluster; the set of graphics cores to offload execution of a second set of instructions associated with ray traversal and/or intersection operations to the scalar cluster; the scalar cluster comprising a plurality of local memories, each local memory associated with one of the scalar execution engines, wherein each local memory is to store a portion of a hierarchical acceleration data structure required by an associated scalar execution engine to execute one or more of the second set of instructions; the plurality of scalar execution engines to store results of the execution of the second set of instructions in a memory accessible by the set of graphics cores; wherein the set of graphics cores are to process the results within the primary graphics thread.
-
公开(公告)号：US20200051309A1
公开(公告)日：2020-02-13
申请号：US16537140
申请日：2019-08-09
Applicant: Intel Corporation
Inventor： HUGUES LABBE , DARREL PALKE , SHERINE ABDELHAK , JILL BOYCE , VARGHESE GEORGE , SCOTT JANUS , ADAM LAKE , ZHIJUN LEI , ZHENGMIN LI , MIKE MACPHERSON , CARL MARSHALL , SELVAKUMAR PANNEER , PRASOONKUMAR SURTI , KARTHIK VEERAMANI , DEEPAK VEMBAR , VALLABHAJOSYULA SRINIVASA SOMAYAZULU
Abstract: One embodiment provides for a graphics processor comprising a block of graphics compute units, a graphics processor pipeline coupled to the block of graphics compute units, and a programmable neural network unit including one or more neural network hardware blocks. The programmable neural network unit is coupled with the block of graphics compute units and the graphics processor pipeline. The one or more neural network hardware blocks include hardware to perform neural network operations and activation operations for a layer of a neural network. The programmable neural network unit can configure settings of one or more hardware blocks within the graphics processor pipeline based on a machine learning model trained to optimize performance of a set of workloads.
-
公开(公告)号：US20220058853A1
公开(公告)日：2022-02-24
申请号：US17500631
申请日：2021-10-13
Applicant: Intel Corporation
Inventor： HUGUES LABBE , DARREL PALKE , SHERINE ABDELHAK , JILL BOYCE , VARGHESE GEORGE , SCOTT JANUS , ADAM LAKE , ZHIJUN LEI , ZHENGMIN LI , MIKE MACPHERSON , CARL MARSHALL , SELVAKUMAR PANNEER , PRASOONKUMAR SURTI , KARTHIK VEERAMANI , DEEPAK VEMBAR , VALLABHAJOSYULA SRINIVASA SOMAYAZULU
Abstract: One embodiment provides for a graphics processor comprising a block of graphics compute units, a graphics processor pipeline coupled to the block of graphics compute units, and a programmable neural network unit including one or more neural network hardware blocks. The programmable neural network unit is coupled with the block of graphics compute units and the graphics processor pipeline. The one or more neural network hardware blocks include hardware to perform neural network operations and activation operations for a layer of a neural network. The programmable neural network unit can configure settings of one or more hardware blocks within the graphics processor pipeline based on a machine learning model trained to optimize performance of a set of workloads.
-
Patent Agency Ranking
公开(公告)号：US20200082059A1
公开(公告)日：2020-03-12
申请号：US16126060
申请日：2018-09-10
Applicant: Intel Corporation
Inventor： BALAJI VEMBU , VIDHYA KRISHNAN , SANDEEP SODHI , SREEKANTH MAVILA , ALTUG KOKER , ADITYA NAVALE , SCOTT JANUS , Changliang WANG
Abstract: Apparatus and method for scalable content protection. For example, one embodiment of an apparatus comprises: cryptographic management circuitry to securely store one or more keys associated with one or more media apps/applications; a plurality of processing engines, each processing engine comprising circuitry to process media content of the one or more media apps/applications; and a scheduler to schedule processing of the media content by the processing engines; wherein the cryptographic management circuitry is to restore a first cryptographic state including a first key associated with a first media app/application and/or first media content responsive to a request to process the first media content on a first processing engine.
-
公开(公告)号：US20250028675A1
公开(公告)日：2025-01-23
申请号：US18791963
申请日：2024-08-01
Applicant: Intel Corporation
Inventor： JOYDEEP RAY , SELVAKUMAR PANNEER , SAURABH TANGRI , BEN ASHBAUGH , SCOTT JANUS , ABHISHEK APPU , VARGHESE GEORGE , RAVISHANKAR IYER , NILESH JAIN , PATTABHIRAMAN K , ALTUG KOKER , MIKE MACPHERSON , JOSH MASTRONARDE , ELMOUSTAPHA OULD-AHMED-VALL , JAYAKRISHNA P. S , ERIC SAMSON
IPC: G06F15/78 , G06F7/544 , G06F7/575 , G06F7/58 , G06F9/30 , G06F9/38 , G06F9/50 , G06F12/02 , G06F12/06 , G06F12/0802 , G06F12/0804 , G06F12/0811 , G06F12/0862 , G06F12/0866 , G06F12/0871 , G06F12/0875 , G06F12/0882 , G06F12/0888 , G06F12/0891 , G06F12/0893 , G06F12/0895 , G06F12/0897 , G06F12/1009 , G06F12/128 , G06F15/80 , G06F17/16 , G06F17/18 , G06N3/08 , G06T1/20 , G06T1/60 , G06T15/06 , H03M7/46
Abstract: Embodiments described herein include software, firmware, and hardware that provides techniques to enable deterministic scheduling across multiple general-purpose graphics processing units. One embodiment provides a multi-GPU architecture with uniform latency. One embodiment provides techniques to distribute memory output based on memory chip thermals. One embodiment provides techniques to enable thermally aware workload scheduling. One embodiment provides techniques to enable end to end contracts for workload scheduling on multiple GPUs.
-
公开(公告)号：US20230360307A1
公开(公告)日：2023-11-09
申请号：US18310015
申请日：2023-05-01
Applicant: Intel Corporation
Inventor： HUGUES LABBE , DARREL PALKE , SHERINE ABDELHAK , JILL BOYCE , VARGHESE GEORGE , SCOTT JANUS , ADAM LAKE , ZHIJUN LEI , ZHENGMIN LI , MIKE MACPHERSON , CARL MARSHALL , SELVAKUMAR PANNEER , PRASOONKUMAR SURTI , KARTHIK VEERAMANI , DEEPAK VEMBAR , VALLABHAJOSYULA SRINIVASA SOMAYAZULU
Abstract: One embodiment provides a graphics processor comprising a block of execution resources, a cache memory, a cache memory prefetcher, and circuitry including a programmable neural network unit, the programmable neural network unit comprising a network hardware block including circuitry to perform neural network operations and activation operations for a layer of a neural network, the programmable neural network unit addressable by cores within the block of graphics cores and the neural network hardware block configured to perform operations associated with a neural network configured to determine a prefetch pattern for the cache memory prefetcher.
-
公开(公告)号：US20220122215A1
公开(公告)日：2022-04-21
申请号：US17428216
申请日：2020-03-14
Applicant: Intel Corporation
Inventor： JOYDEEP RAY , SELVAKUMAR PANNEER , SAURABH TANGRI , BEN ASHBAUGH , SCOTT JANUS , ABHISHEK APPU , VARGHESE GEORGE , RAVISHANKAR IYER , NILESH JAIN , PATTABHIRAMAN K , ALTUG KOKER , MIKE MACPHERSON , JOSH MASTRONARDE , ELMOUSTAPHA OULD-AHMED-VALL , JAYAKRISHNA P. S , ERIC SAMSON
IPC: G06T1/60 , G06F12/06 , G06F12/1009 , G06T1/20 , G06F12/0875 , G06F9/38
Abstract: Embodiments described herein include software, firmware, and hardware that provides techniques to enable deterministic scheduling across multiple general-purpose graphics processing units. One embodiment provides a multi-GPU architecture with uniform latency. One embodiment provides techniques to distribute memory output based on memory chip thermals. One embodiment provides techniques to enable thermally aware workload scheduling. One embodiment provides techniques to enable end to end contracts for workload scheduling on multiple GPUs.
-
公开(公告)号：US20200211263A1
公开(公告)日：2020-07-02
申请号：US16235906
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： SCOTT JANUS , PRASOONKUMAR SURTI , KARTHIK VAIDYANATHAN , ALEXEY SUPIKOV , GABOR LIKTOR , CARSTEN BENTHIN , PHILIP LAWS , MICHAEL DOYLE
Abstract: Apparatus and method for a hierarchical beam tracer. For example, one embodiment of an apparatus comprises: a beam generator to generate beam data associated with a beam projected into a graphics scene; a bounding volume hierarchy (BVH) generator to generate BVH data comprising a plurality of hierarchically arranged BVH nodes; a hierarchical beam-based traversal unit to determine whether the beam intersects a current BVH node and, if so, to responsively subdivide the beam into N child beams to test against the current BVH node and/or to traverse further down the BVH hierarchy to select a new BVH node, wherein the hierarchical beam-based traversal unit is to iteratively subdivide successive intersecting child beams and/or to continue to traverse down the BVH hierarchy until a leaf node is reached with which at least one final child beam is determined to intersect; the hierarchical beam-based traversal unit to generate a plurality of rays within the final child beam; and intersection hardware logic to perform intersection testing for any rays intersecting the leaf node, the intersection testing to determine intersections between the rays intersecting the leaf node and primitives bounded by the leaf node.
-
-
-
-
-
-
-
-
Search Results
9
records
(took 0.013 seconds)
